Resource allocation mechanism for single carrier waveform

ABSTRACT

Systems, apparatuses, methods, and computer-readable media are provided for resource allocation for single carrier waveforms in systems operating at or above 52.6 Gigahertz (GHz) carrier frequencies. Disclosed embodiments include time domain resource allocation techniques and frequency domain resource allocation techniques for systems operating above at or 52.6 GHz carrier frequencies. Other embodiments may be described and/or claimed.

RELATED APPLICATIONS

The present application claims priority to U.S. Provisional App. No.62/747,449, filed Oct. 18, 2018, the contents of which is herebyincorporated by reference in its entirety.

FIELD

Various embodiments of the present application generally relate to thefield of wireless communications, and in particular, to resourceallocation mechanisms for single carrier waveforms for communicationsystems operating above 52.6 GHz.

BACKGROUND

Mobile communication has evolved significantly from early voice systemsto today's highly sophisticated integrated communication platform. Thenext generation wireless communication systems, referred to as FifthGeneration (5G) or new radio (NR) systems, will provide access toinformation and sharing of data anywhere, anytime by various users andapplications. NR is expected to be a unified network/system targeted tomeet vastly different and sometimes conflicting performance dimensionsand services. Such diverse multi-dimensional requirements are driven bydifferent services and applications. In general, NR will evolve based on3GPP LTE-Advanced with additional potential new Radio AccessTechnologies (RATs) to enrich peoples' lives with better, simple andseamless wireless connectivity solutions. NR will enable everything tobe connected by wireless and deliver fast, rich content and services.

In NR Release 15, the system design is based on carrier frequencies upto 52.6 GHz with a waveform choice of cyclic prefix orthogonalfrequency-division multiplexing (CP-OFDM) for downlink (DL) and uplink(UL), and additionally, Discrete Fourier Transform-spread-OFDM(DFT-s-OFDM) for UL. However, for carrier frequency above 52.6 GHz, itis envisioned that a single carrier based waveform is needed in order tohandle issues including low power amplifier (PA) efficiency and largephase noise.

BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 depicts an architecture of a system of a network in accordancewith some embodiments. FIG. 2 illustrates a comparison betweenorthogonal frequency-division multiplexing (OFDM) and single carrierwith frequency domain equalizer (SC-FDE) transmission schemes. FIGS. 3-5illustrate example sub-block structures for single carrier waveformaccording to respective embodiments. FIG. 6 illustrates an example oftime domain resource blocks (TRBs) in one slot according to variousembodiments. FIG. 7 illustrates an example of configured bandwidth parts(BWPs) within system bandwidth (BW) according to various embodiments.

FIG. 8 illustrates an example infrastructure equipment in accordancewith various embodiments. FIG. 9 illustrates an example of a platform inaccordance with various embodiments. FIG. 10 illustrates an example ofcommunication circuitry that may be used to practice the embodimentsdiscussed herein. FIGS. 11 and 12 depict example processes forpracticing the various embodiments discussed herein.

DETAILED DESCRIPTION

Embodiments discussed herein provide resource allocation techniques forsingle carrier waveforms for systems operating above 52.6 Gigahertz(GHz) carrier frequencies. Communication systems operating above the52.6 Gigahertz (GHz) carrier frequency may be referred to herein as“52.6 GHz systems” or the like. In particular, embodiments hereininclude time domain resource allocation techniques for 52.6 GHz systems,and frequency domain resource allocation techniques for 52.6 GHzsystems. Other embodiments may be described and/or claimed.

Referring now to FIG. 1, in which an example architecture of a system100 of a network according to various embodiments, is illustrated. Thefollowing description is provided for an example system 100 thatoperates in conjunction with the Fifth Generation (5G) or New Radio (NR)system standards or Long Term Evolution (LTE) system standards asprovided by 3GPP technical specifications. However, the exampleembodiments are not limited in this regard and the described embodimentsmay apply to other networks that benefit from the principles describedherein, such as future 3GPP systems (e.g., Sixth Generation (6G))systems, IEEE 802.16 protocols (e.g., Wireless Metropolitan Area Network(WMAN), Worldwide Interoperability for Microwave Access (WiMAX), etc.),or the like.

As shown by FIG. 1, the system 100 includes user equipment (UE) 101 aand UE 101 b (collectively referred to as “UEs 101” or “UE 101”). A UE101 is any device with radio communication capabilities, such as awireless communications interface, and describes a remote user ofnetwork resources in a communications network. In this example, UEs 101are illustrated as smartphones, but may also comprise any mobile ornon-mobile computing device, such as consumer tablet computers, wearabledevices, desktop computers, laptop computers, in-vehicle infotainment(IVI) devices, head-up display (HUD) devices, Internet of Things (IoT)devices, embedded systems or microcontrollers, networked or “smart”appliances, and/or the like. The UEs 101 include various hardwareelements such as baseband circuitry, memory circuitry, radiofrequency(RF) circuitry, and interface circuitry (e.g., input/output (I/O)interfaces), some or all of which may be coupled with one another via asuitable interconnect (IX) technology. The RF circuitry includes varioushardware elements (e.g., switches, filters, amplifiers, digital signalprocessors (DSPs), etc.) configured to enable communication withwireless networks using modulated electromagnetic radiation through anon-solid medium. The electronic elements may be arranged as receivesignal path (or receiving (Rx) RF chain) to down-convert received RFsignals and provide baseband signals to the baseband circuitry, andarranged as a transmit signal path to up-convert baseband signalsprovided by the baseband circuitry and provide RF output signals to anantenna array via a front-end module for transmission. The basebandcircuitry and RF circuitry allow the UEs 101 to connect orcommunicatively couple with a Radio Access Network (RAN) 110. In variousembodiments, the UEs 101 may have multiple panels or multiple antennaarrays, and are configured to receive multiple independently scheduleddata streams from different TRPs 111 in a multiple-DCI basedmulti-TRP/panel transmission. These aspects are discussed in more detailinfra.

The UE 101 b is shown to be configured to access an access point (AP)106 via connection 107. The connection 107 can comprise a local wirelessarea network (WLAN) connection consistent with any IEEE 802.11 protocol,wherein the AP 106 may be a WiFi® router, gateway appliance, or thelike. In this example, the AP 106 is shown to be connected to theInternet without connecting to the core network of the wireless system(described in further detail below). In various embodiments, the UE 101b, RAN 110, and AP 106 may be configured to utilize LTE-WLAN aggregation(LWA) operation and/or LTE/WLAN Radio Level Integration with IPsecTunnel (LWIP) operation.

The RAN 110 is a set of RAN nodes 111 that implement a Radio AccessTechnology (RAT); the term “RAT” as used herein refers to a type oftechnology used for radio access such as NR, E-UTRA, WiFi/WLAN, and/orthe like. The set of RAN nodes 111 in the RAN 110 are connected to oneanother via interface 112 and connected to the CN 120 through interface113. In embodiments, the RAN 110 may be a Universal Terrestrial RadioAccess Network (UTRAN) or Groupe Special Mobile (GSM)/Enhanced Dataratesfor GSM (EDGE) RAN (GERAN) when system 100 is an UTRAN or GERAN system,an Evolved UTRAN (E-UTRAN) when system 100 is an LTE or 4G system, or anext generation (NG) RAN or a 5G RAN when system 100 is an NR/5G system.The UEs 101 utilize connections (or channels) 103 and 104, respectively,each of which comprises a physical communications interface or layer.The term “channel” or “link” as used herein refers to any transmissionmedium, either tangible or intangible, which is used to communicate dataor a data stream. Additionally, the term “link” as used herein refers toa connection between two devices through a RAT for the purpose oftransmitting and receiving information. In FIG. 1, the connections 103and 104 are illustrated as an air interface to enable communicativecoupling, and can be consistent with cellular communications protocols,such as GSM, Code-Division Multiple Access (CDMA), Push-to-Talk (PTT)and/or PPT over cellular (POC), UMTS, LTE, 5G/NR, and/or the like. TheUEs 101 may also directly exchange data via a Proximity Services (ProSe)or sidelink (SL) interface 105 comprising one or more physical and/orlogical SL channels.

The RAN 110 includes one or more RAN nodes 111 a and 111 b (collectivelyreferred to as “RAN nodes 111” or “RAN node 111”) that enable theconnections 103 and 104. The RAN nodes 111 are infrastructure equipmentthat provide the radio baseband functions for data and/or voiceconnectivity between a network (e.g., core network (CN) 120) and one ormore users (e.g., UEs 101). The RAN nodes 111 can be referred to asNodeBs 111 in UMTS systems, evolved NodeBs (eNBs) 111 in LTE systems,next generation NodeBs (gNBs) 111 or next generation eNBs (ng-eNBs) in5G/NR systems, Road Side Units (RSUs) for vehicle-to-everything (V2X)implementations, and so forth. In some embodiments, each RAN node 111may be a Transmission/Reception Point (TRP). In other embodiments, eachRAN node 111 may have multiple antenna elements, where each antennaelement may be an individual TRP.

The RAN nodes 111 can comprise ground stations (e.g., terrestrial accesspoints) or satellite stations providing coverage within a geographicarea (e.g., a cell). The RAN nodes 111 may be implemented as one or morededicated physical devices such as a macrocell base stations, and/or alow power base stations for providing femtocells, picocells, or otherlike cells having smaller coverage areas, smaller user capacity, orhigher bandwidth compared to macrocells. Any of the RAN nodes 111 canterminate the air interface protocol and can be the first point ofcontact for the UEs 101. In some embodiments, any of the RAN nodes 111can fulfill various logical functions for the RAN 110 including, but notlimited to, radio network controller (RNC) functions such as radiobearer management, UL and DL dynamic radio resource management and datapacket scheduling, and mobility management.

In some embodiments, all or parts of the RAN nodes 111 may beimplemented as one or more software entities running on server computersas part of a virtual network (e.g., a cloud RAN (CRAN), virtual basebandunit pool (vBBUP), or the like). In these embodiments, the RAN nodes 111may implement a RAN function split where different protocol entities areoperated by different elements. The term “element” as used herein refersto a unit that is indivisible at a given level of abstraction and has aclearly defined boundary. One or more RAN nodes 111 may representindividual distributed units (DUs) that are connected to centralizedunit (CU) via respective F1 interfaces (not shown by FIG. 1). In theseimplementations, the gNB-DUs may include one or more remote radio headsor RFEMs, and the gNB-CU may be operated by a server that is located inthe RAN 110 (not shown) or by a server pool in a similar manner as aCRAN/vBBUP.

The RAN nodes 111 may be configured to communicate with one another viainterface 112. The interface 112 may include a user plane interface forcarrying user plane data between the RAN nodes 111, and a control planeinterface for carrying control signaling between the RAN nodes 111. Theinterface 112 may be an X2 interface 112 when the system 100 is an LTEsystem, and the interface 112 may be an Xn interface 112 when the system100 is a 5G/NR system. In some embodiments, interface 112 may be awireless backhaul connection.

In embodiments, the UEs 101 can be configured to communicate usingOrthogonal Frequency Division Multiplexing (OFDM) communication signalswith each other or with any of the RAN nodes 111 over a multicarriercommunication channel in accordance with various communicationtechniques, such as, but not limited to, an OFDMA communicationtechnique (e.g., for DL communications) or a Single Carrier FrequencyDivision Multiple Access (SC-FDMA) communication technique (e.g., for ULand ProSe/SL communications), although the scope of the embodiments isnot limited in this respect. The OFDM signals can comprise a pluralityof orthogonal subcarriers.

DL and UL transmissions may be organized into frames with 10 msdurations, where each frame includes ten 1 ms subframes, and eachsubframe includes an integer number of slots. Time-frequency radioresource grids may be used to indicate physical resources in the DL orUL in corresponding slots. Each column and each row of the DL resourcegrid corresponds to one OFDM symbol and one OFDM subcarrier,respectively, and each column and each row of the UL resource gridcorresponds to one SC-FDMA symbol and one SC-FDMA subcarrier,respectively. There is one resource grid for a given antenna port p,subcarrier spacing (SCS) configuration and transmission direction (DL orUL). The frequency location of a subcarrier refers to the centerfrequency of that subcarrier. Each element in the resource grid forantenna port p and SCS configuration μ is called a resource element (RE)and is uniquely identified by (k, l)_(p,μ) where k is the index in thefrequency domain (e.g., k is a subcarrier index relative to a referenceor reference point) and l refers to the symbol position in the timedomain relative to some reference point (e.g., l is an OFDM symbol indexrelative to a reference or reference point). RE (k, l)_(p,μ) correspondsto a physical resource and the complex value a_(k,l) ^((p,μ)). In otherwords, a_(k,l) ^((p,μ)) is the value of RE (k, l) for antenna port p andSCS configuration μ. An antenna port is defined such that the channelover which a symbol on the antenna port is conveyed can be inferred fromthe channel over which another symbol on the same antenna port isconveyed. Two antenna ports are said to be quasi co-located (QCLed) ifthe large-scale properties of the channel over which a symbol on oneantenna port is conveyed can be inferred from the channel over which asymbol on the other antenna port is conveyed. The large-scale propertiesinclude one or more of delay spread, Doppler spread, Doppler shift,average gain, average delay, and spatial Rx parameters.

A collection of REs make up a resource block (RB), which is usuallydefined as N_(sc) ^(RB)=12 consecutive subcarriers in the frequencydomain. Physical RBs (PRBs) blocks for subcarrier configuration μ aredefined within a bandwidth part (BWP) and numbered from 0 to N_(BWP,i)^(size,μ)−1 where i is the number of the BWP. Virtual RBs (VRBs) aredefined within a BWP and numbered from 0 to N_(BWP,i) ^(size)−1 where iis the number of the BWP.

A BWP is a subset of contiguous common RBs for a given numerology μ_(i)in BWP i on a given carrier. The UE 101 can be configured with up tofour BWPs in the DL with a single DL BWP being active at a given time.The UE 101 is not expected to receive PDSCH, PDCCH, or CSI-RS (exceptfor RRM) outside an active BWP. The UE 101 can be configured with up tofour BWPs in the UL with a single UL BWP being active at a given time.The UE 101 does not transmit PUSCH or PUCCH outside an active BWP. Foran active cell, the UE 101 does not transmit SRS outside an active BWP.

Common RBs are numbered from 0 and upwards in the frequency domain forSCS configuration μ. The center of subcarrier 0 of common RB 0 for SCSconfiguration μ coincides with ‘point A’. The relation between thecommon RB number n_(CRB) ^(μ) in the frequency domain and resourceelements (k, l) for SCS configuration μ is given by

${n_{{CRB}\;}^{\mu} = \left\lfloor \frac{k}{N_{sc}^{RB}} \right\rfloor},$

where k is defined relative to point A such that k=0 corresponds to thesubcarrier centered around point A.

Point A serves as a common reference point for RB grids and is obtainedfrom the parameters offsetToPointA PCell DL and absoluteFrequencyPointAfor all other cases. The parameter offsetToPointA represents thefrequency offset between point A and the lowest subcarrier of the lowestRB, which has the SCS provided by the higher-layer parametersubCarrierSpacingCommon and overlaps with the SS/PBCH block used by theUE 101 for initial cell selection, expressed in units of RBs assuming 15kHz SCS for FR1 and 60 kHz SCS for FR2. The parameterabsoluteFrequencyPointA for all other cases whereabsoluteFrequencyPointA represents the frequency-location of point Aexpressed as in Absolute Radio-Frequency Channel Number (ARFCN).

There are several different physical channels and physical signals thatare conveyed using RBs, PRBs, and/or individual REs. A physical channelcorresponds to a set of REs carrying information originating from higherlayers. Physical channels include physical UL channels (e.g., physicalUL shared channel (PUSCH), physical UL control channel (PUCCH), physicalrandom access channel (PRACH), etc.) and physical DL channels (e.g.,physical DL shared channel (PDSCH), physical DL control channel (PDCCH),physical broadcast channel (PBCH), etc.). A physical signal is used bythe physical layer (PHY) but does not carry information originating fromhigher layers. Physical signals include physical UL signals (e.g.,Demodulation Reference Signal (DMRS or DM-RS), Phase-Tracking ReferenceSignal (PTRS), Sounding Reference Signal (SRS), etc.) and physical DLsignals (e.g., DMRS, PTRS, Channel State Information Reference Signal(CSI-RS), Primary Synchronization Signal (PSS), SecondarySynchronization Signal (SSS), etc.).

The PDSCH carries user data and higher-layer signaling to the UEs 101,and the PDCCH carries DL resource assignment information for receivingthe PDSCH. Each UE 101 monitors a set of PDCCH candidates on one or moreactivated serving cells as configured by higher layer signaling forcontrol information (e.g., Downlink Control Information (DCI)), wheremonitoring implies attempting to decode a set of PDCCH candidatesaccording one or more monitored DCI formats (e.g., DCI formats 0 through6-2 as discussed in section 5.3.3 of 3GPP TS 38.212 v15.3.0 (2018-09)(hereinafter “TS 38.212 v15.3.0”), DCI formats 0_0 through 2_3 asdiscussed in section 7.3 of TS 38.212 v15.3.0, or the like). The DCIincludes, inter alia, DL assignments and/or UL scheduling grantsincluding, for example, modulation and coding format, resourceallocation, and HARQ information, among other information/commands. EachUE 101 monitors (or attempts to decode) respective sets of PDCCHcandidates in one or more configured monitoring occasions according toUE or cell-specific search spaces (for LTE/4G), or monitors (or attemptsto decode) respective sets of PDCCH candidates in one or more configuredmonitoring occasions in one or more configured Control Resource Sets(CORESETs) according to corresponding search space configurations (forNR/5G). A CORESET includes a set of PRBs with a time duration of 1 to 3OFDM symbols. The REGs and CCEs are defined within a CORESET with eachCCE including a set of REGs. Interleaved and non-interleaved CCE-to-REGmapping are supported in a CORESET. Each REG carrying PDCCH carries itsown DMRS.

PDSCH transmissions are scheduled by DCI format 1_0 and DCI format 1_1.DCI format 1_0 is used for the scheduling of PDSCH in one DL cell andDCI format 1_1 is used for the scheduling of PDSCH in one cell. DCIformat 1_0 includes, inter alia, a frequency domain resource assignment,a time domain resource assignment, and other fields/elements asdiscussed in TS 38.212 v15.3.0. DCI format 1_1 includes, inter alia, abandwidth part indicator, a frequency domain resource assignment, a timedomain resource assignment, antenna port(s) where the number of CDMgroups without data of values 1, 2, and 3 refers to CDM groups {0},{0,1}, and {0, 1, 2} respectively and the antenna ports {p₀, . . . p₀₋₁}are determined according to the ordering of DMRS port(s) given by Tables7.3.1.2.2-1/2/3/4 of TS 38.212 v15.3.0, and other fields/elements asdiscussed in TS 38.212 v15.3.0.

The RAN 110 is shown to be communicatively coupled to a core network(CN) 120 comprising one or more network elements 122, which areconfigured to offer various data and telecommunications services tocustomers/subscribers (e.g., users of UEs 101) who are connected to theCN 120 via the RAN 110. The term “network element” as used herein refersto physical or virtualized equipment and/or infrastructure used toprovide wired or wireless communication network services, and may beconsidered synonymous with, and/or referred to as, a networked computer,networking hardware, network equipment, network node, router, switch,hub, bridge, radio network controller (RNC), RAN device, RAN node,gateway, server, cloud node, Virtualized Network Function (VNF), NFVInfrastructure (NFVI), and/or the like. The network elements 122 may beone or more server computer systems, which may implement various CNelements (e.g., network functions (NFs) and/or application functions(AFs)) such as those discussed herein. The components of the CN 120 maybe implemented in one physical node or separate physical nodes includingcomponents to read and execute instructions from a machine-readable orcomputer-readable medium (e.g., a non-transitory machine-readablestorage medium). In some embodiments, Network Function Virtualization(NFV) may be utilized to virtualize any or all network node functionsvia executable instructions stored in one or more computer-readablestorage mediums (described in further detail below). A logicalinstantiation of the CN 120 may be referred to as a network slice, and alogical instantiation of a portion of the CN 120 may be referred to as anetwork sub-slice. As used herein, the terms “instantiate,”“instantiation,” and the like refers to the creation of an instance, andan “instance” refers to a concrete occurrence of an object, which mayoccur, for example, during execution of program code. NFV architecturesand infrastructures may be used to virtualize one or more networkfunctions, alternatively performed by proprietary hardware, ontophysical resources comprising a combination of industry-standard serverhardware, storage hardware, or switches. In other words, NFV systems canbe used to execute virtual or reconfigurable implementations of one ormore NFs/AFs.

In embodiments where the CN 120 is an Evolved Packet Core (EPC) in LTEsystems, the one or more network elements 122 may include or operate oneor more Mobility Management Entities (MMEs), Serving Gateways (S-GWs),PDN Gateways (P-GWs), Home Subscriber Servers (HSSs), Policy Control andCharging Rules Functions (PCRFs), and/or other like LTE

CN elements. In these embodiments, the E-UTRAN 110 may be connected withthe EPC 120 via an S1 interface 113. In these embodiments, the S1interface 113 is split into two parts: an S1-U interface 114 to carrytraffic data between the RAN nodes 111 and the S-GW, and the S1-MMEinterface 115, which is a signaling interface between the RAN nodes 111and MMEs. Additionally, the P-GW within the EPC 120 may route datapackets between the EPC 120 and external networks such as a networkincluding a Packet Data Network (PDN) 130 via an Internet Protocol (IP)interface 125. The PDN 130 may be an operator external public, a privatePDN (e.g., enterprise network, cloud computing service, etc.), or anintra-operator PDN (e.g., for provision of IMS and/or IP-CAN services).

In embodiments where the CN 120 is a 5GC 120, the network elements 122may implement one or more instances of an Authentication Server Function(AUSF), Access and Mobility Management Function (AMF), SessionManagement Function (SMF), Network Exposure Function (NEF), PolicyControl Function (PCF), NF Repository Function (NRF), Unified DataManagement (UDM) entity, AF, User Plane Function (UPF), Short MessageService Function (SMSF), Non-3GPP Interworking Function (N3IWF), NetworkSlice Selection Function (NSSF), and/or other like NR NFs. In suchembodiments, the NG-RAN 110 may be connected with the 5GC 120 via an NGinterface 113. In these embodiments, the NG interface 113 may be splitinto two parts, an NG-U interface 114, which carries traffic databetween the RAN nodes 111 and a UPF, and the NG-C interface 115, whichis a signaling interface between the RAN nodes 111 and AMFs.Additionally, the UPF within the 5GC 120 may perform packet routing,filtering, inspection, forwarding, etc., between the 5GC 120 andexternal networks such as a data network (DN) 130 via an IP interface125. The DN 130 may represent one or more DNs including one or moreLocal Area DNs (LADNs), and may be an operator external public, aprivate PDN, an intra-operator PDN as discussed previously.

The CN 120 is shown to be communicatively coupled to PDN/DN 130 via anIP communications interface 125. The PDN/DN 130 may include one or moreapplication servers (AS). The application server(s) (and the networkelement(s) 122) comprise one or more physical and/or virtualized systemsfor providing functionality (or services) to one or more clients (e.g.,UEs 101) over a network. Such servers may include various computerdevices with rack computing architecture component(s), tower computingarchitecture component(s), blade computing architecture component(s),and/or the like. The server(s) may represent a cluster of servers, aserver farm, a cloud computing service, or other grouping or pool ofservers, which may be located in one or more datacenters. The server(s)may also be connected to, or otherwise associated with one or more datastorage devices (not shown). Generally, the AS(s) 130 offer applicationsor services that use IP/network resources. As examples, the server(s)may provide traffic management services, cloud computing services,content streaming services, immersive gaming experiences, socialnetworking and/or microblogging services, one or more communicationservices (e.g., VoIP sessions, PTT sessions, group communicationsessions, social networking services, etc.), and/or other like servicesfor the UEs 101 via the CN 120.

FIG. 2 illustrates a comparison between orthogonal frequency-divisionmultiplexing (OFDM) and single carrier with frequency domain equalizer(SC-FDE) transmission schemes. In FIG. 2, the OFDM based transmissionscheme includes DFT-s-OFDM, and a cyclic prefix (CP) is inserted at thebeginning of each data block. The last data symbol(s) in each data blockis/are repeated as the CP. Additionally, a Fast Fourier Transform (FFT)size for the OFDM based transmission scheme includes the data portion ofthe data block. Typically, the length of CP exceeds the maximum expecteddelay spread in order to overcome inter-symbol interference (ISI).

For the SC-FDE transmission scheme, a predetermined sequence, such as aCP, can be inserted into a guard interval (GI) at the beginning of eachdata block, or at both the beginning and end of each data block. Thesequence(s) used for GI may be a unique word (UW), a CP, or some otherknown sequence. The FFT size for the SC-FDE transmission scheme is thedata portion plus the subsequent GI. Further, a linear equalizer in thefrequency domain of the SC-FDE transmission scheme can be employed toreduce receiver (Rx) complexity. Compared to OFDM, the SC-FDEtransmission scheme can reduce Peak to Average Power Ratio (PAPR), whichmay allow the use of a less costly power amplifier.

The GI, UW, or CP is inserted in around the data block in order topartition individual data blocks from one another. Because, in mostimplementations, one data block may have a relatively large numbers ofsamples, in various embodiments, individual data blocks are partitionedinto multiple sub-blocks (see e.g., FIGS. 3-5). Partitioning data blocksinto sub-blocks allows for multiple UEs 101 to be multiplexed within onedata block. For example, when a UE 101 has a relatively small packetsize (e.g., smaller than a preconfigured threshold) for conveying dataor control channel signaling, the whole data block may not be needed fora single carrier waveform (e.g., SC-FDE) transmission. In other words,the data or control channel information may only occupy a partial datablock in various embodiments.

To allow efficient transmission of data or control channel signaling inthe time and frequency domains, certain mechanisms may need to beconsidered for resource allocation for single carrier waveforms (e.g.,SC-FDE waveform). As mentioned previously, the NR Release 15 systemdesign is based on carrier frequencies up to 52.6 GHz with a waveformchoice of CP-OFDM for DL and UL, and DFT-s-OFDM for UL. However, asingle carrier based waveform for carrier frequencies above 52.6 GHz isneeded in order to handle issues related to low power amplifier (PA)efficiency and large phase noise.

Embodiments herein include time domain resource allocation techniquesfor 52.6 GHz systems, and frequency domain resource allocationtechniques for 52.6 GHz systems. Using single carrier waveforms enablesthe network (NW) to configure sub-band based transmissions, whereindividual UEs 101 are assigned or allocated with a certain time and/orfrequency resources for data transmissions above 52.6 GHz. This isdifferent than using OFDM waveforms, which typically utilize an entirebandwidth (BW). These embodiments are discussed in more detail infra.

Time Domain Resource Allocation for 52.6 GHz Systems

As shown by FIG. 2, for single carrier waveform (e.g., SC-FDE waveform),the data transmission is generally block-based. To reduce channelequalization computation costs/overhead, a GI of a known sequence, suchas a UW or CP, is inserted before and after the data block. For thetransmission of data or control channel information with a relativelysmall packet size, the whole data block may not be needed, whichindicates that the data or control channel may only occupy partial datablock. To allow efficient transmission of data or control channelinformation in the time domain, time domain resource allocationembodiments include utilizing a sub-block based structure for singlecarrier waveform transmission schemes (e.g., SC-FDE waveform) for 52.6GHz systems.

FIG. 3 illustrates an example sub-block structure 300 for a singlecarrier waveform according to a first time domain resource allocationembodiment. In this embodiment, a data block is partitioned intomultiple sub-blocks, and no additional GI is inserted in the middle ofthe data block, or between the sub-blocks. Additionally, differentsub-blocks may be assigned or allocated to different UEs 101, which canbe multiplexed in a time division multiplexing (TDM) manner. In theexample of FIG. 3, UE 101 a and UE 101 b are allocated respectivesub-blocks of equal size. Further, the GI is only inserted before andafter the data block, and no GI is inserted between the two sub-blocks.With the transmission block structure of the first embodiment, each UE101 may process the whole data block in order to access its ownsub-block(s). This embodiment may be appropriate for PDCCH and/or PDSCHtransmissions with a small payload size such as, for example, a pagingmessage or short message of a paging channel carried by PDSCH can betransmitted in one sub-block.

FIG. 4 illustrates an example sub-block structure 400 for a singlecarrier waveform according to a second time domain resource allocationembodiment. In this embodiment, one data block is partitioned intomultiple sub-blocks, each of which has its own GIs at both sides of thedata portion of the sub-block. In the example of FIG. 4, UE 101 a and UE101 b are allocated respective sub-blocks of equal size, where a firstGI (01) is inserted at the beginning of the data block (e.g., at thebeginning of the sub-block for UE 101 a), a second GI (GI2) is insertedbetween the two sub-blocks, and a third GI (GI3) is inserted at the endof the data block (e.g., at the end of the sub-block for UE 101 b). Thisblock structure is suitable for both DL or UL transmissions with a smallpacket/payload size, for low capability UEs 101 such as IoT UEs 101. ForUL transmissions, a gap may or may not be added between two adjacent GIs(e.g., a fourth GI (GI4) of another data block (not shown by FIG. 4)after GI3). If the gap is inserted, the gap can be used to absorb thetime synchronization (sync) error of the related UEs 101. Further, thissub-block structure can be used for the transmission of PUCCH format 0or 1.

FIG. 5 illustrates an example sub-block structure 500 for a singlecarrier waveform according to a third time domain resource allocationembodiment. In this embodiment, separate GIs are inserted before andafter each sub-block.

Although the embodiments shown and described with respect to FIGS. 3-5only show two sub-blocks, the embodiments herein are not limited todividing blocks into two sub-blocks. In various embodiments, individualblocks may be divided into more sub-blocks than shown by FIGS. 3-5.

In any of the aforementioned embodiments, the GIs, the GI embodiment tobe used (e.g., as discussed with respect to FIGS. 3-5), the size ofsub-blocks, or sets of sub-block sizes may be configured via higherlayer signaling. For example, such a configuration may be signaled tothe UEs 101 via NR minimum system information (MSI) signaling, NRremaining minimum system information (RMSI) signaling, NR other systeminformation (OSI) signaling, radio resource control (RRC) signaling,medium access control-control element (MAC-CE) signaling, and/ordynamically indicated by DCI. For example, a set of the sub-block sizesmay be configured via dedicated RRC signaling, and DCI may be signaledto the UE 101 to activate one sub-block size of the set of sub-blocksizes to be used for reception of PDSCH and/or transmission of PUSCH. Insuch embodiments, a new or existing field in the DCI format may be usedto indicate the sub-block size to be used from the set of the sub-blocksizes.

In some embodiments, a time domain resource allocation can be defined atthe block level, sub-block level, or according to time domain resourceblocks (TRBs). Where TRBs are used, aspects of the TRBs can bepredefined or configured via higher layers, for example, using MSI,RMSI, OSI, or RRC signaling. Additionally, the TRBs can be expressed intime units T_(c)=1/Δf_(max)·N_(f) where Δf_(max) is a maximum SCS whereΔf_(max)=1920·10³ Hz, and N_(f)=4096. In some embodiments, the TRB isdefined in terms of the number of samples in the time domain based on areference sampling rate, or in terms of the time unit T_(c) (see e.g.,section 4.1 of 3GPP TS 38.211 v15.3.0 (2018-09) (hereinafter “TS38.211”)).

FIG. 6 illustrates an example Time domain Resource Block (TRB) scheme600 according to various embodiments. FIG. 6 shows N number of TRBs(labeled 0 to (N−1)) in one slot, where Nis a number. In thisembodiment, the number of TRBs in a slot, N, can be determined based onthe slot duration and/or the size of the TRBs. Additionally, a TRB canbe assigned to either a GI or a UE's 101 data. In some embodiments, someof the TRBs including the first TRBs and/or the last TRBs may be usedfor the GI.

In one embodiment, a start and length indicator value (SLIV) can beemployed for the time domain resource allocation for single carrierwaveform for 52.6 GHz systems. For example, when the UE 101 is scheduledto receive PDSCH by downlink control information (DCI), the Time domainresource assignment field value m of the DCI provides a row index m+1 toan allocation table. The determination of the used resource allocationtable is defined in subclause 5.1.2.1.1 of 3GPP TS 38.214 v15.2.0(2018-06) (hereinafter “TS 38.214”). The indexed row defines the slotoffset K₀, the start and length indicator SLIV, or directly the startsymbol S and the allocation length L, and the PDSCH mapping type to beassumed in the PDSCH reception. Given the parameter values of theindexed row: the slot allocated for the PDSCH is

${\left\lfloor {n \cdot \frac{2^{\mu_{PDSCH}}}{2^{\mu_{PDDCH}}}} \right\rfloor + K_{0}},$

where n is the slot with the scheduling DCI, and K₀ is based on thenumerology of PDSCH, and μ_(PDSCH) and μ_(PDDCH) are the SCSconfigurations for PDSCH and PDCCH, respectively, and the startingsymbol S relative to the start of the slot, and the number ofconsecutive symbols L counting from the symbol S allocated for the PDSCHare determined from the start and length indicator SLIV: if (L−1)≤7 thenSLIV=14·(L−1)+S; else SLIV=14·(14−L+1)+(14−1−S), where 0<L≤14−S, and thePDSCH mapping type is set to Type A or Type B as defined in Subclause7.4.1.1.2 of TS 38.211.

In another example, when the UE 101 is scheduled to transmit a transportblock and no CSI report, or the UE 101 is scheduled to transmit atransport block and a CSI report(s) on PUSCH by a DCI, the Time domainresource assignment field value m of the DCI provides a row index m+1 toan allocated table. The determination of the used resource allocationtable is defined in subclause 6.1.2.1.1 of TS 38.214. The indexed rowdefines the slot offset K₂, the start and length indicator SLIV, ordirectly the start symbol S and the allocation length L, and the PUSCHmapping type to be applied in the PUSCH transmission. When the UE 101 isscheduled to transmit a PUSCH with no transport block and with a CSIreport(s) by a CSI request field on a DCI, the Time-domain resourceassignment field value m of the DCI provides a row index m+1 to anallocated table which is defined by the higher layer configuredpusch-TimeDomainAllocationList in pusch-Config. The indexed row definesthe start and length indicator SLIV, and the PUSCH mapping type to beapplied in the PUSCH transmission and the K2 value is determined as

${K_{2} = \begin{matrix}{\max\;{Y_{j}\left( {m + 1} \right)}} \\j\end{matrix}},$

where Y_(j), j=0, . . . , N_(Rep) ⁻¹ are the corresponding list entriesof the higher layer parameter reportSlotOffsetList in CSI-ReportConfigfor the N_(Rep) triggered CSI Reporting Settings and Y_(j)(m+1) is the(m+1)th entry of Y_(j). The slot where the UE 101 shall transmit thePUSCH is determined by

${K_{2}\mspace{14mu}{as}\mspace{14mu}\left\lfloor {n \cdot \frac{2^{\mu_{PDSCH}}}{2^{\mu_{PDDCH}}}} \right\rfloor} + K_{2}$

where n is the slot with the scheduling DCI, K₂ is based on thenumerology of PUSCH, and μ_(PUSCH) and μ_(PDCCH) are the SCSconfigurations for PUSCH and PDCCH, respectively, and the startingsymbol S relative to the start of the slot, and the number ofconsecutive symbols L counting from the symbol S allocated for the PUSCHare determined from the start and length indicator SLIV of the indexedrow: if (L−1)≤7 then SLIV=14·(L−1)+S; else SLIV=14·(14−L+1)+(14−1−S),where 0<L≤14−S, and the PUSCH mapping type is set to Type A or Type B asdefined in Subclause 6.4.1.1.3 of TS 38.211 as given by the indexed row.

Further, in some embodiments, the granularity may be based on a TRB, aTRB Group (TBG), a sub-block, or a block instead of an OFDM symbol. EachTBG includes M TRBs, where M is a predefined number of TRBs or M is aconfigured number of TRBs indicated via by higher layers, such as theMSI, RMSI, OSI, or RRC signaling. In these embodiments, the start symbolS and the allocation length L of a data transmission (e.g., a PDSCH/PUSCH transmission) with their GIs can be indicated in terms of TRBs, TBGs,sub-block(s), or data block(s). Additionally or alternatively, the SLIVmay be used to indicate the start symbol S and the allocation length Lof a TRB including the one or more GIs.

In one example, the UE 101 determines the SLIV based on the DCI (or thetime domain resource allocation field in the DCI), and from the SLIV,the UE 101 determines a start TRB (e.g., “TRBs”) and an allocationlength L of the data transmission, where the allocation length L is anumber of consecutive TRBs counting from the start TRBs. In thisexample, the start TRBs may be a starting or leading GI at the beginningof a data block (or sub-block), and a last TRB in the consecutive TRBsmay be an ending GI for the data block (or sub-block).

In another example, the UE 101 determines the SLIV based on the DCI (orthe time domain resource allocation field in the DCI), and from theSLIV, the UE 101 determines a start symbol S and an allocation length Lof the data transmission, where the allocation length L is a number ofconsecutive symbols of one or more TRBs counting from the start symbolS. In this example, a first number of symbols starting with the startsymbol S may be a starting or leading GI at the beginning of a datablock (or sub-block), and one or more ending symbols in the consecutivesymbols may be an ending GI for the data block (or sub-block).

In other embodiments, a bitmap based time domain resource allocation canbe employed for single carrier waveform for 52.6 GHz systems. In suchembodiments, the DL/UL resource allocation type 0 for frequency domainresource allocation can be straightforwardly extended and employed. Inthese embodiments, each bit in the bitmap represents a correspondingTRB, a corresponding TBG, a corresponding sub-block, or a correspondingdata block in the time domain.

In one example, in DL resource allocation type 0, the RB assignmentinformation includes a bitmap indicating the Resource Block Groups(RBGs) that are allocated to the scheduled UE 101 where a RBG is a setof consecutive VRBs defined by higher layer parameter rbg-Sizeconfigured by PDSCH-Config and the size of the BWP as defined in Table5.1.2.2.1-1 of TS 38.214. Similarly, for UL resource allocation of type0, the RB assignment information includes a bitmap indicating the RBGsthat are allocated to the scheduled UE 101 where a RBG is a set ofconsecutive VRBs defined by higher layer parameter rbg-Size configuredby pusch-Config and the size of the BWP as defined in Table 6.1.2.2.1-1of TS 38.214. In this example for either DL or UL, one or more VRBs inthe RBGs correspond(s) to a TRB, a TBG, a sub-block, or data block.

In another example, in DL resource allocation type 0, the RB assignmentinformation includes a bitmap indicating the TBGs that are allocated toa scheduled UE 101 where a TBG is a set of consecutive TRBs defined by asuitable higher layer parameter (e.g., trb-Size) configured by asuitable configuration (e.g., PDSCH-Config and/or the like) and the sizeof a BWP. Similarly, for UL resource allocation type 0, the RBassignment information includes a bitmap indicating the TBGs that areallocated to a scheduled UE 101 where a TBG is a set of consecutive TRBsdefined by a suitable higher layer parameter (e.g., trb-Size) configuredby a suitable configuration (e.g., PUSCH-Config for PUSCH and/or thelike) and the size of a BWP. In this example for either DL or UL, theTRBs may have a same or similar definition as defined for RBGs as shownby Table 5.1.2.2.1-1 and/or Table 6.1.2.2.1-1 of TS 38.214.

In another example, in DL resource allocation type 0, the RB assignmentinformation includes a bitmap indicating the data blocks that areallocated to a scheduled UE 101 where a data block is a set ofconsecutive sub-blocks defined by a suitable higher layer parameterconfigured by a suitable configuration (e.g., PDSCH-Config for PDSCHand/or the like) and the size of a BWP. Similarly, for UL resourceallocation type 0, the RB assignment information includes a bitmapindicating the data blocks that are allocated to a scheduled UE 101where a data block is a set of consecutive sub-blocks defined by asuitable higher layer parameter configured by a suitable configuration(e.g., PUSCH-Config for PUSCH and/or the like) and the size of a BWP. Inthis example, the data blocks may have a same or similar definition asdefined for RBGs as shown by Table 5.1.2.2.1-1 and/or Table 6.1.2.2.1-1of TS 38.214.

In any of the aforementioned examples, the bitmap for UL and/or DL maybe of size M_(TBG) bits with one bitmap bit per TBG such that each TBGis addressable. In some embodiments, the TBGs may be indexed in theorder of increasing frequency and starting at the lowest frequency ofthe BWP. In these embodiments, the order of the TBG bitmap is such thatTBG 0 to TBG M_(TBG)−1 are mapped from MSB to LSB, and the TBG isallocated to the UE 101 if the corresponding bit value in the bitmap is1, the TBG is not allocated to the UE 101 otherwise.

Frequency Time Domain Resource Allocation for 52.6 GHz Systems

FIG. 7 illustrates an example 700 of configured BWPs within system BW,according to various embodiments. In NR systems, BWPs allow limitedcapability UEs 101 to access the network. Limited capability UEs 101 mayrefer to low complexity devices (e.g., IoT UEs 101) and/or UEs 101 withlimited radio frequency (RF) BW. A BWP includes a group of contiguousPRBs. As shown by FIG. 7, the BW of a BWP is equal to, or is smallerthan each UE's 101 maximum BW capability, and is at least as large assynchronization signal block (SSB) BW. Further, one BWP is configuredwith a numerology including an SCS and CP.

A UE 101 can be configured with up to four DL BWPs with a single DL BWPbeing active at a given time for a cell or carrier, and a UE 101 can beconfigured with up to four UL BWPs with a single uplink BWP active at agiven time for a cell or carrier. The UE 101 is not expected to receivePDSCH, PDCCH, or CSI-RS (except for RRM) outside an active BWP, and theUE 101 does not transmit PUSCH or PUCCH outside an active BWP. The UE101 may receive the PDCCH within a narrower BWP in order to reduce powerconsumption. Subsequently, the UE 101 may switch to a BWP with a largerBW such as when a high data rate transmission has been scheduled. Byemploying BWP switching, UE 101 power consumption can be reduced.

The UE 101 determines the frequency domain RB assignment using theresource allocation field (e.g., frequency domain resource assignmentfield) in a detected DCI carried by PDCCH except for PUSCH transmissionsscheduled by a Random Access Response (RAR) UL grant, in which case thefrequency domain resource allocation is determined according tosubclause 8.3 of 3GPP TS 38.213 v15.3.0 (2018-09) (hereinafter “TS38.213”). As an example, the detected DCI may be DCI format 1_0 or DCIformat 1_1 as discussed by sections 7.3.1.2.1 and 7.3.1.2.2 of TS38.212, respectively.

As alluded to previously, there are two DL and UL resource allocationschemes, type 0 and type 1. The UE 101 assumes that when the schedulinggrant is received with DCI format 1_0, then the DL resource allocationtype 1 is used. If the scheduling DCI is configured to indicate the DLresource allocation type as part of the Frequency domain resourceassignment field by setting a higher layer parameter resourceAllocationin pdsch-Config to ‘dynamicswitch’, the UE 101 uses DL resourceallocation type 0 or type 1 as defined by the Frequency domain resourceassignment field in the DCI. Otherwise, the UE 101 uses the DL frequencyresource allocation type as defined by the higher layer parameterresourceAllocation.

For UL resource allocation schemes, UL resource allocation scheme type 0is supported for PUSCH only when transform precoding is disabled, andtype 1 is supported for PUSCH for both cases when transform precoding isenabled or disabled. If the scheduling DCI is configured to indicate theUL resource allocation type as part of the Frequency domain resourceassignment field by setting a higher layer parameter resourceAllocationin pusch-Config to ‘dynamicSwitch’, the UE 101 uses uplink resourceallocation type 0 or type 1 as defined by the Frequency domain resourceassignment field in the DCI. Otherwise, the UE 101 uses the uplinkfrequency resource allocation type as defined by the higher layerparameter resourceAllocation. The UE shall assume that when thescheduling PDCCH is received with DCI format 0_0, then uplink resourceallocation type 1 is used.

If a bandwidth part indicator field is not configured in the schedulingDCI or the UE 101 does not support active BWP change via DCI, the RBindexing for DL or UL type 0 and type 1 resource allocation isdetermined within the UE's 101 active BWP. If a bandwidth part indicatorfield is configured in the scheduling DCI and the UE 101 supports activeBWP change via DCI, the RB indexing for DL or UL type 0 and type 1resource allocation is determined within the UE's 101 BWP indicated bythe bandwidth part indicator field value in the DCI. Upon detection ofPDCCH intended for the UE 101, the UE 101 first determines the DLbandwidth part and then determines the resource allocation within theBWP. At least for the UL, RB numbering starts from the lowest RB in thedetermined UL BWP.

For DL and UL resource allocation type 0, the RB assignment informationincludes a bitmap indicating the RBGs that are allocated to thescheduled UE 101 where an RBG is a set of consecutive VRBs defined byhigher layer parameter rbg-Size configured by PDSCH-Config for the DL orconfigured by pusch-Config for the UL, and the size of the BWP asdefined in Table 5.1.2.2.1-1 of TS 38.214 for DL or defined in Table6.1.2.2.1-1 of TS 38.214 for UL. For DL and UL resource allocation type1, the RB assignment information indicates to the scheduled UE 101 a setof contiguously allocated non-interleaved or interleaved VRBs within theactive BWP of size N_(BWP) ^(size) PRBs.

For 52.6 GHz systems, a BWP can be supported to allow limited capabilityUEs 101 to access the network, and to reduce UE 101 power consumption.However, for single carrier waveform (e.g., SC-FDE waveforms), thefrequency domain resource allocation in terms of PRBs may not be needed.In this case, to allow multiple UEs 101 to access the networksimultaneously, frequency domain resource allocation embodiments forsingle carrier waveform transmission schemes (e.g., SC-FDE waveform) in52.6 GHz systems are as follows:

In one frequency domain resource allocation embodiment, the UE 101 canbe configured with multiple BWPs, where one BWP in the DL and/or one BWPin the UL can be active for a given time in a component cell (CC) (orcomponent carrier (CC)). The physical channels and signals fully occupythe active BWP. In this embodiment, a frequency domain resourceassignment field for specific PBRs in the DCI used to dynamicallyschedule PDSCH and/or PUSCH may not be needed, and as such, thesePRB-related fields may be removed or omitted from the DCI. For example,the VRB-to-PRB mapping field, a PRB bundling size field, and/or afrequency hopping field may be removed or omitted from the DCI. Further,for configured grant PUSCH transmissions, the parameters related tofrequency resource allocation such as resourceAllocation, rbg-Size,frequencyDomainAllocation, frequencyHoppingOffset, and frequencyHoppingmay not be needed in the RRC configuration message.

In another embodiment, the UE 101 may be configured with multiple BWPs,where one BWP in DL and/or UL can be activated in a CC for one or moreUE 101 antenna port groups. In this embodiment, each antenna port groupcorresponds to a transmission or reception panel. This embodiment mayalso be applied to carriers below 52.6 GHz and/or other waveforms (e.g.,CP-OFDM and DFT-s-OFDM) as well as 52.6 GHz systems and single carrierwaveform (e.g., SC-FDE waveforms).

In another embodiment, the BW of a BWP can be a fraction of the systemBW. For example, the BW of a BWP can be defined as:

${BW_{BWP}} = \frac{BW_{Sys}}{K}$

In the above equation, BW_(BWP) is the BW of a BWP, BW_(Sys) is thesystem BW and K is an integer. In one example, K=2^(n), where n is aninteger.

To indicate the location of a BWP for a given UE 101, point A can bedefined and employed for single carrier waveform for 52.6 GHz systems.Further, the starting location of the configured BWP can be defined asan absolution frequency distance (e.g., in MHz) relative to point A. Toreduce the signaling overhead, the value K as mentioned previously canbe indicated/signaled to the UE 101 in the DCI and/or in a high layerconfiguration. In this embodiment, the UE 101 determines the BW of theBWP based on the indicated K value.

Example Systems and Implementations

Each of the UEs 101, RAN nodes 111, AP 106, network element(s) 122,application servers 130, and/or any other device or system discussedpreviously with respect to FIGS. 1-7 may include various hardware and/orsoftware elements, such as those discussed infra with respect to FIG. 8and XS2.

FIG. 8 illustrates an example of infrastructure equipment 800 inaccordance with various embodiments. The infrastructure equipment 800(or “system 800”) may be implemented as a base station, radio head, RANnode such as the RAN nodes 111 and/or AP 106 shown and describedpreviously, application server(s) 130, and/or any other element/devicediscussed herein. In other examples, the system 800 could be implementedin or by a UE.

The system 800 includes application circuitry 805, baseband circuitry810, one or more radio front end modules (RFEMs) 815, memory circuitry820, power management integrated circuitry (PMIC) 825, power teecircuitry 830, network controller circuitry 835, network interfaceconnector 840, satellite positioning circuitry 845, and user interface850. In some embodiments, the device 800 may include additional elementssuch as, for example, memory/storage, display, camera, sensor, orinput/output (I/O) interface. In other embodiments, the componentsdescribed below may be included in more than one device. For example,said circuitries may be separately included in more than one device forCRAN, vBBU, or other like implementations. The term “circuitry” as usedherein refers to a circuit or system of multiple circuits configured toperform a particular function in an electronic device. The circuit orsystem of circuits may be part of, or include one or more hardwarecomponents, such as logic circuits, processor(s) (shared, dedicated, orgroup) and/or memory (shared, dedicated, or group), Integrated Circuits(ICs), Application-specific ICs (ASICs), Field Programmable Gate Arrays(FPGAs), Digital Signal Processors (DSPs), etc., that are configured toprovide the described functionality. In addition, the term “circuitry”may also refer to a combination of one or more hardware elements withthe program code used to carry out the functionality of that programcode. Some types of circuitry may execute one or more software orfirmware programs to provide at least some of the describedfunctionality. Such a combination of hardware elements and program codemay be referred to as a particular type of circuitry. The term“processor circuitry” as used herein refers to, is part of, or includescircuitry capable of sequentially and automatically carrying out asequence of arithmetic or logical operations, or recording, storing,and/or transferring digital data. and/or any other device capable ofexecuting or otherwise operating computer-executable instructions, suchas program code, software modules, and/or functional processes. As usedherein, the term “module” refers to one or more independent electroniccircuits packaged onto a circuit board, FPGA, ASIC, SoC, SiP, etc.,configured to provide a basic function within a computer system. A“module” may include a processor circuitry (shared, dedicated, or group)and/or memory circuitry shared, dedicated, or group), etc., that executeone or more software or firmware programs, a combinational logiccircuit, and/or other suitable components that provide the describedfunctionality. As used herein, the term “interface circuitry” refers to,is part of, or includes circuitry providing for the exchange ofinformation between two or more components or devices. The term“interface circuitry” refers to one or more hardware interfaces, forexample, buses, input/output (I/O) interfaces, peripheral componentinterfaces, network interface cards, and/or the like.

Application circuitry 805 includes circuitry such as, but not limited toone or more processors (or processor cores), cache memory, and one ormore of low drop-out voltage regulators (LDOs), interrupt controllers,serial interfaces such as SPI, I²C or universal programmable serialinterface module, real time clock (RTC), timer-counters includinginterval and watchdog timers, general purpose input/output (I/O or IO),memory card controllers such as Secure Digital (SD) MultiMediaCard (MMC)or similar, Universal Serial Bus (USB) interfaces, Mobile IndustryProcessor Interface (MIPI) interfaces and Joint Test Access Group (JTAG)test access ports. The processors (or cores) of the applicationcircuitry 805 may be coupled with or may include memory/storage elementsand may be configured to execute instructions stored in thememory/storage to enable various applications or operating systems torun on the system 800. In some implementations, the memory/storageelements may be on-chip memory circuitry, which may include any suitablevolatile and/or non-volatile memory, such as DRAM, SRAM, EPROM, EEPROM,Flash memory, solid-state memory, and/or any other type of memory devicetechnology, such as those discussed herein.

The processor(s) of application circuitry 805 may include, for example,one or more processor cores (CPUs), one or more application processors,one or more graphics processing units (GPUs), one or more reducedinstruction set computing (RISC) processors, one or more Acorn RISCMachine (ARM) processors, one or more complex instruction set computing(CISC) processors, one or more digital signal processors (DSP), one ormore FPGAs, one or more PLDs, one or more ASICs, one or moremicroprocessors or controllers, or any suitable combination thereof. Insome embodiments, the application circuitry 805 may comprise, or may be,a special-purpose processor/controller to operate according to thevarious embodiments herein. As examples, the processor(s) of applicationcircuitry 805 may include one or more Intel Pentium®, Core®, or Xeon®processor(s); Advanced Micro Devices (AMD) Ryzen® processor(s),Accelerated Processing Units (APUs), or Epyc® processors; ARM-basedprocessor(s) licensed from ARM Holdings, Ltd. such as the ARM Cortex-Afamily of processors and the ThunderX2® provided by Cavium™, Inc.; aMIPS-based design from MIPS Technologies, Inc. such as MIPS WarriorP-class processors; and/or the like. In some embodiments, the system 800may not utilize application circuitry 805, and instead may include aspecial-purpose processor/controller to process IP data received from anEPC or 5GC, for example.

In some implementations, the application circuitry 805 may include oneor more hardware accelerators, which may be microprocessors,programmable processing devices, or the like. The one or more hardwareaccelerators may include, for example, computer vision (CV) and/or deeplearning (DL) accelerators. As examples, the programmable processingdevices may be one or more a field-programmable devices (FPDs) such asfield-programmable gate arrays (FPGAs) and the like; programmable logicdevices (PLDs) such as complex PLDs (CPLDs), high-capacity PLDs(HCPLDs), and the like; ASICs such as structured ASICs and the like;programmable SoCs (PSoCs); and the like. In such implementations, thecircuitry of application circuitry 805 may comprise logic blocks orlogic fabric, and other interconnected resources that may be programmedto perform various functions, such as the procedures, methods,functions, etc. of the various embodiments discussed herein. In suchembodiments, the circuitry of application circuitry 805 may includememory cells (e.g., erasable programmable read-only memory (EPROM),electrically erasable programmable read-only memory (EEPROM), flashmemory, static memory (e.g., static random access memory (SRAM),anti-fuses, etc.)) used to store logic blocks, logic fabric, data, etc.in look-up-tables (LUTs) and the like.

The baseband circuitry 810 may be implemented, for example, as asolder-down substrate including one or more integrated circuits, asingle packaged integrated circuit soldered to a main circuit board or amulti-chip module containing two or more integrated circuits. Thebaseband circuitry 810 includes one or more processing devices (e.g.,baseband processors) to carry out various protocol and radio controlfunctions. Baseband circuitry 810 may interface with applicationcircuitry of system 800 for generation and processing of basebandsignals and for controlling operations of the RFEMs 815. The basebandcircuitry 810 may handle various radio control functions that enablecommunication with one or more radio networks via the RFEMs 815. Thebaseband circuitry 810 may include circuitry such as, but not limitedto, one or more single-core or multi-core processors (e.g., one or morebaseband processors) or control logic to process baseband signalsreceived from a receive signal path of the RFEMs 815, and to generatebaseband signals to be provided to the RFEMs 815 via a transmit signalpath. In various embodiments, the baseband circuitry 810 may implement aRTOS to manage resources of the baseband circuitry 810, schedule tasks,etc. Examples of the RTOS may include Operating System Embedded (OSE)™provided by Enea®, Nucleus RTOS™ provided by Mentor Graphics®, VersatileReal-Time Executive (VRTX) provided by Mentor Graphics®, ThreadX™provided by Express Logic®, FreeRTOS, REX OS provided by Qualcomm®, OKL4provided by Open Kernel (OK) Labs®, or any other suitable RTOS, such asthose discussed herein.

User interface circuitry 850 may include one or more user interfacesdesigned to enable user interaction with the system 800 or peripheralcomponent interfaces designed to enable peripheral component interactionwith the system 800. User interfaces may include, but are not limitedto, one or more physical or virtual buttons (e.g., a reset button), oneor more indicators (e.g., light emitting diodes (LEDs)), a physicalkeyboard or keypad, a mouse, a touchpad, a touchscreen, speakers orother audio emitting devices, microphones, a printer, a scanner, aheadset, a display screen or display device, etc. Peripheral componentinterfaces may include, but are not limited to, a nonvolatile memoryport, a universal serial bus (USB) port, an audio jack, a power supplyinterface, etc.

The radio front end modules (RFEMs) 815 may comprise a millimeter wave(mmWave) RFEM and one or more sub-mmWave radio frequency integratedcircuits (RFICs). In some implementations, the one or more sub-mmWaveRFICs may be physically separated from the mmWave RFEM. The RFICs mayinclude connections to one or more antennas or antenna arrays, and theRFEM may be connected to multiple antennas. In alternativeimplementations, both mmWave and sub-mmWave radio functions may beimplemented in the same physical RFEM 815, which incorporates bothmmWave antennas and sub-mmWave.

The memory circuitry 820 may include one or more of volatile memoryincluding dynamic random access memory (DRAM) and/or synchronous dynamicrandom access memory (SDRAM), and nonvolatile memory (NVM) includinghigh-speed electrically erasable memory (commonly referred to as Flashmemory), phase change random access memory (PRAM), magnetoresistiverandom access memory (MRAM), etc., and may incorporate thethree-dimensional (3D) cross-point (XPOINT) memories from Intel® andMicron®. Memory circuitry 820 may be implemented as one or more ofsolder down packaged integrated circuits, socketed memory modules andplug-in memory cards.

The PMIC 825 may include voltage regulators, surge protectors, poweralarm detection circuitry, and one or more backup power sources such asa battery or capacitor. The power alarm detection circuitry may detectone or more of brown out (under-voltage) and surge (over-voltage)conditions. The power tee circuitry 830 may provide for electrical powerdrawn from a network cable to provide both power supply and dataconnectivity to the infrastructure equipment 800 using a single cable.

The network controller circuitry 835 may provide connectivity to anetwork using a standard network interface protocol such as Ethernet,Ethernet over GRE Tunnels, Ethernet over Multiprotocol Label Switching(MPLS), or some other suitable protocol. Network connectivity may beprovided to/from the infrastructure equipment 800 via network interfaceconnector 840 using a physical connection, which may be electrical(commonly referred to as a “copper interconnect”), optical, or wireless.The network controller circuitry 835 may include one or more dedicatedprocessors and/or FPGAs to communicate using one or more of theaforementioned protocols. In some implementations, the networkcontroller circuitry 835 may include multiple controllers to provideconnectivity to other networks using the same or different protocols.

The positioning circuitry 845 includes circuitry to receive and decodesignals transmitted/broadcasted by a positioning network of a globalnavigation satellite system (GNSS). Examples of navigation satelliteconstellations (or GNSS) include United States' Global PositioningSystem (GPS), Russia's Global Navigation System (GLONASS), the EuropeanUnion's Galileo system, China's BeiDou Navigation Satellite System, aregional navigation system or GNSS augmentation system (e.g., Navigationwith Indian Constellation (NAVIC), Japan's Quasi-Zenith Satellite System(QZSS), France's Doppler Orbitography and Radio-positioning Integratedby Satellite (DORIS), etc.), or the like. The positioning circuitry 845comprises various hardware elements (e.g., including hardware devicessuch as switches, filters, amplifiers, antenna elements, and the like tofacilitate OTA communications) to communicate with components of apositioning network, such as navigation satellite constellation nodes.In some embodiments, the positioning circuitry 845 may include aMicro-Technology for Positioning, Navigation, and Timing (Micro-PNT) ICthat uses a master timing clock to perform position tracking/estimationwithout GNSS assistance. The positioning circuitry 845 may also be partof, or interact with, the baseband circuitry 810 and/or RFEMs 815 tocommunicate with the nodes and components of the positioning network.The positioning circuitry 845 may also provide position data and/or timedata to the application circuitry 805, which may use the data tosynchronize operations with various infrastructure (e.g., RAN nodes 111,etc.), or the like.

The components shown by FIG. 8 may communicate with one another usinginterface circuitry 806 or IX 806, which may include any number of busand/or IX technologies such as Industry Standard Architecture (ISA),extended ISA, inter-integrated circuit (I²C), Serial PeripheralInterface (SPI), point-to-point interfaces, power management bus(PMBus), Peripheral Component Interconnect (PCI), PCI express (PCIe),PCI extended (PCIx), Intel® Ultra Path Interconnect (UPI), Intel®Accelerator Link (IAL), Coherent Accelerator Processor Interface (CAPI),OpenCAPI™, Intel® QuickPath Interconnect (QPI), Intel® Omni-PathArchitecture (OPA) IX, RapidIO™ system IXs, Cache Coherent Interconnectfor Accelerators (CCIX), Gen-Z Consortium IXs, a HyperTransport IX,NVLink provided by NVIDIA®, and/or any number of other IX technologies.Additionally or alternatively, the IX technology may be a proprietarybus, for example, used in an SoC based system.

FIG. 9 illustrates an example of a platform 900 (or “device 900”) inaccordance with various embodiments. In embodiments, the computerplatform 900 may be suitable for use as UEs 101, application servers130, and/or any other element/device discussed herein. The platform 900may include any combinations of the components shown in the example. Thecomponents of platform 900 may be implemented as integrated circuits(ICs), portions thereof, discrete electronic devices, or other modules,logic, hardware, software, firmware, or a combination thereof adapted inthe computer platform 900, or as components otherwise incorporatedwithin a chassis of a larger system. Some of the components shown may beomitted, additional components may be present, and different arrangementof the components shown may occur in other implementations.

Application circuitry 905 includes circuitry such as, but not limited toone or more processors (or processor cores), cache memory, and one ormore of LDOs, interrupt controllers, serial interfaces such as SPI, I²Cor universal programmable serial interface module, RTC, timer-countersincluding interval and watchdog timers, general purpose I/O, memory cardcontrollers such as SD MMC or similar, USB interfaces, MIPI interfaces,and JTAG test access ports. The processors (or cores) of the applicationcircuitry 905 may be coupled with or may include memory/storage elementsand may be configured to execute instructions stored in thememory/storage to enable various applications or operating systems torun on the system 900. In some implementations, the memory/storageelements may be on-chip memory circuitry, which may include any suitablevolatile and/or non-volatile memory, such as DRAM, SRAM, EPROM, EEPROM,Flash memory, solid-state memory, and/or any other type of memory devicetechnology, such as those discussed herein.

The processor(s) of application circuitry 805 may include, for example,one or more processor cores, one or more application processors, one ormore GPUs, one or more RISC processors, one or more ARM processors, oneor more CISC processors, one or more DSP, one or more FPGAs, one or morePLDs, one or more ASICs, one or more microprocessors or controllers, amultithreaded processor, an ultra-low voltage processor, an embeddedprocessor, some other known processing element, or any suitablecombination thereof. In some embodiments, the application circuitry 805may comprise, or may be, a special-purpose processor/controller tooperate according to the various embodiments herein.

As examples, the processor(s) of application circuitry 905 may includean Intel® Architecture Core™ based processor, such as a Quark™, anAtom™, an i3, an i5, an i7, or an MCU-class processor, or another suchprocessor available from Intel® Corporation, Santa Clara, Calif. Theprocessors of the application circuitry 905 may also be one or more ofAdvanced Micro Devices (AMD) Ryzen® processor(s) or AcceleratedProcessing Units (APUs); A5-A9 processor(s) from Apple® Inc.,Snapdragon™ processor(s) from Qualcomm® Technologies, Inc., TexasInstruments, Inc.® Open Multimedia Applications Platform (OMAP)™processor(s); a MIPS-based design from MIPS Technologies, Inc. such asMIPS Warrior M-class, Warrior I-class, and Warrior P-class processors;an ARM-based design licensed from ARM Holdings, Ltd., such as the ARMCortex-A, Cortex-R, and Cortex-M family of processors; or the like. Insome implementations, the application circuitry 905 may be a part of asystem on a chip (SoC) in which the application circuitry 905 and othercomponents are formed into a single integrated circuit, or a singlepackage, such as the Edison™ or Galileo™ SoC boards from Intel®Corporation.

Additionally or alternatively, application circuitry 905 may includecircuitry such as, but not limited to, one or more a field-programmabledevices (FPDs) such as FPGAs and the like; programmable logic devices(PLDs) such as complex PLDs (CPLDs), high-capacity PLDs (HCPLDs), andthe like; ASICs such as structured ASICs and the like; programmable SoCs(PSoCs); and the like. In such embodiments, the circuitry of applicationcircuitry 905 may comprise logic blocks or logic fabric, and otherinterconnected resources that may be programmed to perform variousfunctions, such as the procedures, methods, functions, etc. of thevarious embodiments discussed herein. In such embodiments, the circuitryof application circuitry 905 may include memory cells (e.g., erasableprogrammable read-only memory (EPROM), electrically erasableprogrammable read-only memory (EEPROM), flash memory, static memory(e.g., static random access memory (SRAM), anti-fuses, etc.)) used tostore logic blocks, logic fabric, data, etc. in look-up tables (LUTs)and the like.

The baseband circuitry 910 may be implemented, for example, as asolder-down substrate including one or more integrated circuits, asingle packaged integrated circuit soldered to a main circuit board or amulti-chip module containing two or more integrated circuits. Thevarious hardware electronic elements of baseband circuitry 910 arediscussed infra with regard to Figure XT.

The RFEMs 915 may comprise a millimeter wave (mmWave) RFEM and one ormore sub-mmWave radio frequency integrated circuits (RFICs). In someimplementations, the one or more sub-mmWave RFICs may be physicallyseparated from the mmWave RFEM. The RFICs may include connections to oneor more antennas or antenna arrays (see e.g., antenna array XT111 ofFigure XT infra), and the RFEM may be connected to multiple antennas. Inalternative implementations, both mmWave and sub-mmWave radio functionsmay be implemented in the same physical RFEM 915, which incorporatesboth mmWave antennas and sub-mmWave.

The memory circuitry 920 may include any number and type of memorydevices used to provide for a given amount of system memory. Asexamples, the memory circuitry 920 may include one or more of volatilememory including random access memory (RAM), dynamic RAM (DRAM) and/orsynchronous dynamic RAM (SDRAM), and nonvolatile memory (NVM) includinghigh-speed electrically erasable memory (commonly referred to as Flashmemory), phase change random access memory (PRAM), magnetoresistiverandom access memory (MRAM), etc. The memory circuitry 920 may bedeveloped in accordance with a Joint Electron Devices EngineeringCouncil (JEDEC) low power double data rate (LPDDR)-based design, such asLPDDR2, LPDDR3, LPDDR4, or the like. Memory circuitry 920 may beimplemented as one or more of solder down packaged integrated circuits,single die package (SDP), dual die package (DDP) or quad die package(Q17P), socketed memory modules, dual inline memory modules (DIMMs)including microDIMMs or MiniDIMMs, and/or soldered onto a motherboardvia a ball grid array (BGA). In low power implementations, the memorycircuitry 920 may be on-die memory or registers associated with theapplication circuitry 905. To provide for persistent storage ofinformation such as data, applications, operating systems and so forth,memory circuitry 920 may include one or more mass storage devices, whichmay include, inter alia, a solid state disk drive (SSDD), hard diskdrive (HDD), a micro HDD, resistance change memories, phase changememories, holographic memories, or chemical memories, among others. Forexample, the computer platform 900 may incorporate the three-dimensional(3D) cross-point (XPOINT) memories from Intel® and Micron®.

Removable memory circuitry 923 may include devices, circuitry,enclosures/housings, ports or receptacles, etc. used to couple portabledata storage devices with the platform 900. These portable data storagedevices may be used for mass storage purposes, and may include, forexample, flash memory cards (e.g., Secure Digital (SD) cards, microSDcards, xD picture cards, and the like), and USB flash drives, opticaldiscs, external HDDs, and the like.

The platform 900 may also include interface circuitry (not shown) thatis used to connect external devices with the platform 900. The externaldevices connected to the platform 900 via the interface circuitryinclude sensor circuitry 921 and electro-mechanical components (EMCs)922, as well as removable memory devices coupled to removable memorycircuitry 923.

The sensor circuitry 921 include devices, modules, or subsystems whosepurpose is to detect events or changes in its environment and send theinformation (sensor data) about the detected events to some other adevice, module, subsystem, etc. Examples of such sensors include, interalia, inertia measurement units (IMUs) comprising accelerometers,gyroscopes, and/or magnetometers; microelectromechanical systems (MEMS)or nanoelectromechanical systems (NEMS) comprising 3-axisaccelerometers, 3-axis gyroscopes, and/or magnetometers; level sensors;flow sensors; temperature sensors (e.g., thermistors); pressure sensors;barometric pressure sensors; gravimeters; altimeters; image capturedevices (e.g., cameras or lensless apertures); light detection andranging (LiDAR) sensors; proximity sensors (e.g., infrared radiationdetector and the like), depth sensors, ambient light sensors, ultrasonictransceivers; microphones or other like audio capture devices; etc.

The actuators 922, allow platform 900 to change its state, position,and/or orientation, or move or control a mechanism or system. Theactuators 922 comprise electrical and/or mechanical devices for movingor controlling a mechanism or system, and converts energy (e.g.,electric current or moving air and/or liquid) into some kind of motion.The actuators 922 may include one or more electronic (orelectrochemical) devices, such as piezoelectric biomorphs, solid stateactuators, solid state relays (SSRs), shape-memory alloy-basedactuators, electroactive polymer-based actuators, relay driverintegrated circuits (ICs), and/or the like. The actuators 922 mayinclude one or more electromechanical devices such as pneumaticactuators, hydraulic actuators, electromechanical switches includingelectromechanical relays (EMRs), motors (e.g., DC motors, steppermotors, servomechanisms, etc.), wheels, thrusters, propellers, claws,clamps, hooks, an audible sound generator, and/or other likeelectromechanical components. The platform 900 may be configured tooperate one or more actuators 922 based on one or more captured eventsand/or instructions or control signals received from a service providerand/or various client systems.

In some implementations, the interface circuitry may connect theplatform 900 with positioning circuitry 945. The positioning circuitry945 includes circuitry to receive and decode signalstransmitted/broadcasted by a positioning network of a GNSS. Examples ofnavigation satellite constellations (or GNSS) include United States'GPS, Russia's GLONASS, the European Union's Galileo system, China'sBeiDou Navigation Satellite System, a regional navigation system or GNSSaugmentation system (e.g., NAVIC), Japan's QZSS, France's DORIS, etc.),or the like. The positioning circuitry 945 comprises various hardwareelements (e.g., including hardware devices such as switches, filters,amplifiers, antenna elements, and the like to facilitate OTAcommunications) to communicate with components of a positioning network,such as navigation satellite constellation nodes. In some embodiments,the positioning circuitry 945 may include a Micro-PNT IC that uses amaster timing clock to perform position tracking/estimation without GNSSassistance. The positioning circuitry 945 may also be part of, orinteract with, the baseband circuitry 810 and/or RFEMs 915 tocommunicate with the nodes and components of the positioning network.The positioning circuitry 945 may also provide position data and/or timedata to the application circuitry 905, which may use the data tosynchronize operations with various infrastructure (e.g., radio basestations), for turn-by-turn navigation applications, or the like

In some implementations, the interface circuitry may connect theplatform 900 with Near-Field Communication (NFC) circuitry 940. NFCcircuitry 940 is configured to provide contactless, short-rangecommunications based on radio frequency identification (RFID) standards,wherein magnetic field induction is used to enable communication betweenNFC circuitry 940 and NFC-enabled devices external to the platform 900(e.g., an “NFC touchpoint”). NFC circuitry 940 comprises an NFCcontroller coupled with an antenna element and a processor coupled withthe NFC controller. The NFC controller may be a chip/IC providing NFCfunctionalities to the NFC circuitry 940 by executing NFC controllerfirmware and an NFC stack. The NFC stack may be executed by theprocessor to control the NFC controller, and the NFC controller firmwaremay be executed by the NFC controller to control the antenna element toemit short-range RF signals. The RF signals may power a passive NFC tag(e.g., a microchip embedded in a sticker or wristband) to transmitstored data to the NFC circuitry 940, or initiate data transfer betweenthe NFC circuitry 940 and another active NFC device (e.g., a smartphoneor an NFC-enabled POS terminal) that is proximate to the platform 900.

The driver circuitry 946 may include software and hardware elements thatoperate to control particular devices that are embedded in the platform900, attached to the platform 900, or otherwise communicatively coupledwith the platform 900. The driver circuitry 946 may include individualdrivers allowing other components of the platform 900 to interact withor control various input/output (I/O) devices that may be presentwithin, or connected to, the platform 900. For example, driver circuitry946 may include a display driver to control and allow access to adisplay device, a touchscreen driver to control and allow access to atouchscreen interface of the platform 900, sensor drivers to obtainsensor readings of sensor circuitry 921 and control and allow access tosensor circuitry 921, EMC drivers to obtain actuator positions of theEMCs 922 and/or control and allow access to the EMCs 922, a cameradriver to control and allow access to an embedded image capture device,audio drivers to control and allow access to one or more audio devices.

The power management integrated circuitry (PMIC) 925 (also referred toas “power management circuitry 925”) may manage power provided tovarious components of the platform 900. In particular, with respect tothe baseband circuitry 910, the PMIC 925 may control power-sourceselection, voltage scaling, battery charging, or DC-to-DC conversion.The PMIC 925 may often be included when the platform 900 is capable ofbeing powered by a battery 930, for example, when the device is includedin a UE 101.

In some embodiments, the PMIC 925 may control, or otherwise be part of,various power saving mechanisms of the platform 900. For example, if theplatform 900 is in an RRC_Connected state, where it is still connectedto the RAN node as it expects to receive traffic shortly, then it mayenter a state known as Discontinuous Reception Mode (DRX) after a periodof inactivity. During this state, the platform 900 may power down forbrief intervals of time and thus save power. If there is no data trafficactivity for an extended period of time, then the platform 900 maytransition off to an RRC_Idle state, where it disconnects from thenetwork and does not perform operations such as channel qualityfeedback, handover, etc. The platform 900 goes into a very low powerstate and it performs paging where again it periodically wakes up tolisten to the network and then powers down again. The platform 900 maynot receive data in this state; in order to receive data, it musttransition back to RRC_Connected state. An additional power saving modemay allow a device to be unavailable to the network for periods longerthan a paging interval (ranging from seconds to a few hours). Duringthis time, the device is totally unreachable to the network and maypower down completely. Any data sent during this time incurs a largedelay and it is assumed the delay is acceptable.

A battery 930 may power the platform 900, although in some examples theplatform 900 may be mounted deployed in a fixed location, and may have apower supply coupled to an electrical grid. The battery 930 may be alithium ion battery, a metal-air battery, such as a zinc-air battery, analuminum-air battery, a lithium-air battery, and the like. In someimplementations, such as in V2X applications, the battery 930 may be atypical lead-acid automotive battery.

In some implementations, the battery 930 may be a “smart battery,” whichincludes or is coupled with a Battery Management System (BMS) or batterymonitoring integrated circuitry. The BMS may be included in the platform900 to track the state of charge (SoCh) of the battery 930. The BMS maybe used to monitor other parameters of the battery 930 to providefailure predictions, such as the state of health (SoH) and the state offunction (SoF) of the battery 930. The BMS may communicate theinformation of the battery 930 to the application circuitry 905 or othercomponents of the platform 900. The BMS may also include ananalog-to-digital (ADC) convertor that allows the application circuitry905 to directly monitor the voltage of the battery 930 or the currentflow from the battery 930. The battery parameters may be used todetermine actions that the platform 900 may perform, such astransmission frequency, network operation, sensing frequency, and thelike.

A power block, or other power supply coupled to an electrical grid maybe coupled with the BMS to charge the battery 930. In some examples, thepower block XS30 may be replaced with a wireless power receiver toobtain the power wirelessly, for example, through a loop antenna in thecomputer platform 900. In these examples, a wireless battery chargingcircuit may be included in the BMS. The specific charging circuitschosen may depend on the size of the battery 930, and thus, the currentrequired. The charging may be performed using the Airfuel standardpromulgated by the Airfuel Alliance, the Qi wireless charging standardpromulgated by the Wireless Power Consortium, or the Rezence chargingstandard promulgated by the Alliance for Wireless Power, among others.

User interface circuitry 950 includes various input/output (I/O) devicespresent within, or connected to, the platform 900, and includes one ormore user interfaces designed to enable user interaction with theplatform 900 and/or peripheral component interfaces designed to enableperipheral component interaction with the platform 900. The userinterface circuitry 950 includes input device circuitry and outputdevice circuitry. Input device circuitry includes any physical orvirtual means for accepting an input including, inter alia, one or morephysical or virtual buttons (e.g., a reset button), a physical keyboard,keypad, mouse, touchpad, touchscreen, microphones, scanner, headset,and/or the like. The output device circuitry includes any physical orvirtual means for showing information or otherwise conveyinginformation, such as sensor readings, actuator position(s), or otherlike information. Output device circuitry may include any number and/orcombinations of audio or visual display, including, inter alia, one ormore simple visual outputs/indicators (e.g., binary status indicators(e.g., light emitting diodes (LEDs)) and multi-character visual outputs,or more complex outputs such as display devices or touchscreens (e.g.,Liquid Chrystal Displays (LCD), LED displays, quantum dot displays,projectors, etc.), with the output of characters, graphics, multimediaobjects, and the like being generated or produced from the operation ofthe platform 900. The output device circuitry may also include speakersor other audio emitting devices, printer(s), and/or the like. In someembodiments, the sensor circuitry 921 may be used as the input devicecircuitry (e.g., an image capture device, motion capture device, or thelike) and one or more EMCs may be used as the output device circuitry(e.g., an actuator to provide haptic feedback or the like). In anotherexample, NFC circuitry comprising an NFC controller coupled with anantenna element and a processing device may be included to readelectronic tags and/or connect with another NFC-enabled device.Peripheral component interfaces may include, but are not limited to, anon-volatile memory port, a USB port, an audio jack, a power supplyinterface, etc.

The components shown by FIG. 9 may communicate with one another usinginterface circuitry 906 or IX 906, which may include any number of busand/or IX technologies such as ISA, extended ISA, I²C, SPI,point-to-point interfaces, PMBus, PCI, PCIe, PCIx, Intel® UPI, Intel®IAL, Intel® CXL, CAPI, OpenCAPI, Intel® QPI, Intel® UPI, Intel® OPA IX,RapidIO™ system IXs, CCIX, Gen-Z Consortium IXs, a HyperTransportinterconnect, NVLink provided by NVIDIA®, a Time-Trigger Protocol (TTP)system, a FlexRay system, and/or any number of other IX technologies.Additionally or alternatively, the IX technology may be a proprietarybus, for example, used in an SoC based system.

FIG. 10 illustrates an example of communication circuitry 1000 that maybe used to practice the embodiments discussed herein. Components asshown by FIG. 10 are shown for illustrative purposes and may includeother components not shown by FIG. 10, or the elements shown by FIG. 10may by alternatively be grouped according to functions.

The communication circuitry 1000 includes protocol processing circuitry1005, which operates or implements various protocol layers/entities ofone or more wireless communication protocols. In one example, theprotocol processing circuitry 1005 may operate Long Term Evolution (LTE)protocol entities and/or Fifth Generation (5G)/New Radio (NR) protocolentities when the communication circuitry 1000 is a cellularradiofrequency communication system, such as millimeter wave (mmWave)communication circuitry or some other suitable cellular communicationcircuitry. In this example, the protocol processing circuitry 1005 wouldoperate medium access control (MAC), radio link control (RLC), packetdata convergence protocol (PDCP), service data adaptation protocol(SDAP), radio resource control (RRC), and non-access stratum (NAS)functions. In another example, the protocol processing circuitry 1005may operate one or more IEEE-based protocols when the communicationcircuitry 1000 is WiFi communication system. In this example, theprotocol processing circuitry 1005 would operate MAC and logical linkcontrol (LLC) functions.

The protocol processing circuitry 1005 may include one or more memorystructures (not shown) to store program code and data information foroperating the protocol functions, as well as one or more processingcores (not shown) to execute the program code and perform variousoperations using the data information. The protocol processing circuitry1005 may include one or more instances of control circuitry (not shown)to provide control functions for the digital baseband circuitry 1010,transmit circuitry 1015, receive circuitry 1020, and/or radiofrequency(RF) circuitry 1025. In some embodiments, the protocol processingcircuitry 1005 and/or the baseband circuitry 1010 correspond to thebaseband circuitry 810 and 910 of FIGS. 8 and 9, respectively.

The communication circuitry 1000 also includes digital basebandcircuitry 1010, which implements physical layer (PHY) functionsincluding hybrid automatic repeat request (HARQ) functions, scramblingand/or descrambling, (en)coding and/or decoding, layer mapping and/orde-mapping, modulation symbol mapping, received symbol and/or bit metricdetermination, multi-antenna port pre-coding and/or decoding which mayinclude one or more of space-time, space-frequency or spatial coding,reference signal generation and/or detection, preamble sequencegeneration and/or decoding, synchronization sequence generation and/ordetection, control channel signal blind decoding, radio frequencyshifting, and other related functions. The modulation/demodulationfunctionality may include Fast-Fourier Transform (FFT), precoding, orconstellation mapping/demapping functionality. The encoding/decodingfunctionality may include convolution, tail-biting convolution, turbo,Viterbi, Low Density Parity Check (LDPC) coding, polar coding, etc.Embodiments of modulation/demodulation and encoder/decoder functionalityare not limited to these examples and may include other suitablefunctionality in other embodiments.

Baseband processing circuitry 1010 and/or protocol processing circuitry1005 may interface with an application platform (e.g., applicationcircuitry 805 or application circuitry 905 of FIGS. 8 and 9,respectively) for generation and processing of baseband signals and forcontrolling operations of the RF circuitry 1025. The digital basebandcircuitry 1010 may handle various radio control functions that enablecommunication with one or more radio networks via the RF circuitry 1025.The digital baseband circuitry 1010 may include circuitry such as, butnot limited to, one or more single-core or multi-core processors (e.g.,one or more baseband processors) or control logic to process basebandsignals received from a receive signal path of the RF circuitry 1025(e.g., via Rx circuitry 1020) and to generate baseband signals for atransmit signal path of the RF circuitry 1025 (e.g., via Tx circuitry1015). The digital baseband circuitry 1010 may comprise a multi-protocolbaseband processor or the like.

As mentioned previously, the digital baseband circuitry 1010 may includeor implement encoder circuitry, which accepts input data, generatesencoded data based on the input data, and outputs the encoded data to amodulation mapper. The encoder may also perform one or more of errordetecting, error correcting, rate matching, and interleaving. Theencoder may further include scrambling based on a scrambling sequencesuch as those discussed herein. The digital baseband circuitry 1010 mayinclude or implement a sequence generator to generate, for example, lowPeak to Average Power Ratio (low-PAPR) sequences (see e.g., section5.2.2 of TS 38.211), pseudo-random noise (PN) sequences (see e.g.,section 5.2.1 of TS 38.211), and/or reference signal sequences. In someembodiments, the sequence generator may be a part of the encodercircuitry.

The digital baseband circuitry 1010 may include or implement amodulation mapper that takes binary digits as input (e.g., the encodeddata from the encoder) and produces complex-valued modulation symbols asan output. The modulation mapper may operate one or more suitablemodulation schemes, such as those discussed by, for example, section 5.1of TS 38.211. The modulation mapper may map groups containing one ormore binary digits, selected from the encoded data, to complex valuedmodulation symbols according to one or more mapping tables. Thecomplex-valued modulation symbols may be input to a layer mapper to bemapped to one or more layer mapped modulation symbol streams (see e.g.,sections 6.3.1.3 and 7.3.1.3 of TS 38.211). The one or more streams oflayer mapped symbols may be input to precoder that generates one or morestreams of precoded symbols, which may be represented as a block ofvectors. The precoder may be configured to perform a direct mappingusing a single antenna port, transmit diversity using space-time blockcoding, or spatial multiplexing. Each stream of precoded symbols may beinput to a resource mapper that generates a stream of resource mappedsymbols (e.g., REs). The resource mapper may map precoded symbols tofrequency domain subcarriers and time domain symbols according to amapping, which may include contiguous block mapping, randomized mapping,and/or sparse mapping according to a mapping code.

The digital baseband circuitry 1010 may also include or implement abaseband signal generator (also referred to as a “multicarriergenerator”) to generate OFDM baseband signals and/or other basebandsignals. In these embodiments, the resource mapped symbols from theresource mapper are input to the baseband signal generator whichgenerates time domain baseband symbol(s). The baseband signal generatormay generate a time domain signal (e.g., a set of time domain symbols)using, for example, an inverse discrete Fourier transform, commonlyimplemented as an inverse fast Fourier transform (IFFT) or a filter bankcomprising one or more filters. The time-domain signal that results fromthe IFFT is transmitted across the radio channel. At the receiver, anFFT block is used to process the received signal and bring it into thefrequency domain which is used to recover the original data bits.Other/additional aspects of the operation of the digital basebandcircuitry 1010 are discussed by TS 38.211.

The communication circuitry 1000 also includes transmit (Tx) circuitry1015 and receive (Rx) circuitry 1020. The Tx circuitry 1015 isconfigured to convert digital baseband signals into analog signals fortransmission by the RF circuitry 1025. To do so, in one embodiment, theTx circuitry 1015 includes various components, such as digital to analogconverters (DACs), analog baseband circuitry, up-conversion circuitry,and filtering and amplification circuitry. Additionally oralternatively, the Tx circuitry 1015 may include digital transmitcircuitry and output circuitry.

The Rx circuitry 1020 is configured to convert analog signals receivedby the RF circuitry 1025 into digital baseband signals to be provided tothe digital baseband circuitry 1010. To do so, in one embodiment, the Rxcircuitry 1020 includes parallel receive circuitry and/or one or moreinstances of combined receive circuitry. The parallel receive circuitryand instances of the combined receive circuitry may include IntermediateFrequency (IF) down-conversion circuitry, IF processing circuitry,baseband down-conversion circuitry, baseband processing circuitry, andanalog-to-digital converter (ADC) circuitry.

The communication circuitry 1000 also includes radiofrequency (RF)circuitry 1025 to enable communication with wireless networks usingmodulated electromagnetic radiation through a non-solid medium. The RFcircuitry 1025 includes a receive signal path, which may includecircuitry to convert analog RF signals (e.g., an existing or receivedmodulated waveform) into digital baseband signals to be provided to thedigital baseband circuitry 1010 via the Rx circuitry 1020. The RFcircuitry 1025 also includes a transmit signal path, which may includecircuitry configured to convert digital baseband signals provided by thedigital baseband circuitry 1010 via the Tx circuitry 1015 to beconverted into analog RF signals (e.g., modulated waveform) that will beamplified and transmitted via the antenna array 1030.

RF circuitry 1025 may include one or more instances of radio chaincircuitry, which may include one or more filters, power amplifiers, lownoise amplifiers, programmable phase shifters, and power supplies (notshown). RF circuitry 1025 may also include power combining and dividingcircuitry. The power combining and dividing circuitry may operatebidirectionally, such that the same physical circuitry may be configuredto operate as a power divider when the device is transmitting, and as apower combiner when the device is receiving. In some embodiments, thepower combining and dividing circuitry may include wholly or partiallyseparate circuitries to perform power dividing when the device istransmitting and power combining when the device is receiving. The powercombining and dividing circuitry may include passive circuitrycomprising one or more two-way power divider/combiners arranged in atree. In some embodiments, the power combining and dividing circuitrymay include active circuitry comprising amplifier circuits.

The communication circuitry 1000 also includes antenna array 1030. Theantenna array 1030 include one or more antenna elements. The antennaarray 1030 may be a plurality of microstrip antennas or printed antennasthat are fabricated on the surface of one or more printed circuitboards. The antenna array 1030 may be formed in as a patch of metal foil(e.g., a patch antenna) in a variety of shapes, and may be coupled withthe RF circuitry 1025 using metal transmission lines or the like.

FIGS. 11 and 12 show example procedures 1100 and 1200, respectively, inaccordance with various embodiments. For illustrative purposes, thevarious operations of process 1100 is described as being performed by aUE 101 or elements thereof, and process 1200 is described as beingperformed by a RAN node 111. In some embodiments, the processes 1100 and1200 may be embodied as one or more computer readable storage mediacomprising program code, instructions, or other like a computer programproduct (or data to create the computer program product), which is tocause a computing device (e.g., UE 101 or RAN node 111) to performelectronic operations and/or to perform the specific sequence or flow ofactions described with respect to FIGS. 11 and 12. While particularexamples and orders of operations are illustrated FIGS. 11 and 12, thedepicted orders of operations should not be construed to limit the scopeof the embodiments in any way. Rather, the depicted operations may bere-ordered, broken into additional operations, combined, and/or omittedaltogether while remaining within the spirit and scope of the presentdisclosure.

FIG. 11 depicts an example process 1100 according to variousembodiments. Process 1100 begins at operation 1105 where the UE 101 (orbaseband circuitry of the UE 101) determines, based on a receivedconfiguration for a single carrier waveform at or above 52.6 GHz,configured time domain resources and configured frequency domainresources. At operation 1110, the UE 101 (or baseband circuitry of theUE 101) determines, based on received DCI, a time domain resourceallocation and/or a frequency domain resource allocation fortransmitting or receiving a data transmission (e.g., a PDSCH or PUSCHtransmission). At operation 1115, the UE 101 (or RF circuitry of the UE101) transmits or receives the data transmission according to the timedomain resource allocation and the frequency domain resource allocation.The configured time domain resources and the time domain resourceallocation may be the same or similar to the embodiments discussedpreviously with respect to FIGS. 3-6, and the configured frequencydomain resources and the frequency domain resource allocation may be thesame or similar to the embodiments discussed previously with respect toFIG. 7. After operation 1115, process 1100 ends or repeats as necessary.

FIG. 12 depicts an example process 1200 according to variousembodiments. Process 1200 begins at operation 1205 where a RAN node 111(or application circuitry and/or baseband circuitry of the RAN node 111)generates a configuration message for a single carrier waveform systemoperating at or above 52.6 GHz to indicate configured time domainresources and configured frequency domain resources. At operation 1210,the RAN node 111 (or RFEM(s) of the RAN node 111) transmits theconfiguration message to a UE 101 via higher layer signaling. At somelater point, at operation 1215, the RAN node 111 (or applicationcircuitry and/or baseband circuitry of the RAN node 111) generates DCIto indicate a time domain resource allocation and a frequency domainresource allocation for transmitting or receiving a data transmission.At operation 1220, the RAN node 111 (or RFEM(s) of the RAN node 111)transmits the DCI to the UE 101 to indicate activated ones of theconfigured time domain resources and configured frequency domainresources. The configured time domain resources and the time domainresource allocation may be the same or similar to the embodimentsdiscussed previously with respect to FIGS. 3-6, and the configuredfrequency domain resources and the frequency domain resource allocationmay be the same or similar to the embodiments discussed previously withrespect to FIG. 7. After operation 1215, process 1200 ends or repeats asnecessary.

Some non-limiting examples are as follows. The following examplespertain to further embodiments, and specifics in the examples may beused anywhere in one or more embodiments discussed previously. Any ofthe following examples may be combined with any other example or anyembodiment discussed herein.

Example A01 includes a method of operating a System-on-Chip (SoC) to beimplemented in a user equipment (UE) capable of communicating atfrequencies above 52.6 gigahertz (GHz), the method comprising:determining, by baseband circuitry of the SoC based on Downlink ControlInformation (DCI) received via radiofrequency (RF) circuitry, a resourceallocation for a data transmission scheduled by the DCI, the datatransmission having a single carrier waveform at or above 52.6 GHz; andcontrolling, by the baseband circuitry, the RF circuitry via interfacecircuitry of the SoC to transmit or receive the data transmissionaccording to the determined resource allocation, the interface circuitrycommunicatively coupling the baseband circuitry with the RF circuitry.

Example A02 includes the method of example A01, wherein the singlecarrier waveform includes a plurality of blocks where each block of theplurality of blocks includes a data portion and at least one guardinterval (GI) positioned before the data portion and/or at least one GIpositioned after the data portion, wherein the data portion of eachblock is divided into at least two sub-blocks, and wherein the datatransmission is to take place within a sub-block of a block of theplurality of blocks.

Example A03 includes the method of example A02, wherein no GI is to bepositioned between each sub-block of the at least two sub-blocks, onlyone GI is to be positioned between each sub-block of the at least twosub-blocks, or a GI is to be positioned before and after each sub-blockof the at least two sub-blocks, such that two GIs are positioned betweeneach sub-block.

Example A04 includes the method of example A03, wherein the GI is toinclude a unique word or a cyclic prefix.

Example A05 includes the method of example A04, wherein the resourceallocation is to indicate a sub-block in which the data transmission isto be transmitted or received.

Example A06 includes the method of example A05, further comprising:determining, by the baseband circuitry based on higher layer signalingreceived via the RF circuitry, a GI configuration and one or moresub-block sizes, wherein the DCI is to indicate a selected sub-blocksize of the one or more sub-block sizes; and controlling, by thebaseband circuitry, the RF circuitry via the interface circuitry totransmit or receive the data transmission during a time periodcorresponding to the selected sub-block size.

Example A07 includes the method of examples A01-A06, wherein the singlecarrier waveform includes a plurality of time domain resource blocks(TRBs) and the method further comprises: determining, by the basebandcircuitry based on higher layer signaling received via the RF circuitry,a configuration that indicates N number of TRBs, wherein the DCI is toindicate one or more selected TRBs of the N number of TRBs; andcontrolling, by the baseband circuitry, the RF circuitry via theinterface circuitry to transmit or receive the data transmission duringone or more time units T_(c) corresponding to the one or more selectedTRBs.

Example A08 includes the method of example A07, wherein theconfiguration is to indicate one or more TRBs of the N number of TRBs tobe used as GIs.

Example A09 includes the method of examples A07-A08, wherein the methodfurther comprises: determining, by the baseband circuitry, the N numberof TRBs based on a slot duration or a TRB size indicated by theconfiguration.

Example A10 includes the method of examples A07-A09, wherein theresource allocation is a time domain resource allocation, and the methodfurther comprises: determining, by the baseband circuitry based on atime domain resource assignment field in the DCI, a starting TRBrelative to a start of a slot in which the data transmission is to betransmitted or received and an allocation length, wherein the allocationlength is a number of consecutive TRBs counting from the starting TRB,and the number of consecutive TRBs are the one or more selected TRBs.

Example A11 includes the method of examples A07-A10, wherein theresource allocation is a time domain resource allocation, and the methodfurther comprises: determining, by the baseband circuitry, a bitmapbased on a time domain resource assignment field in the DCI, wherein thebitmap is to indicate the one or more selected TRBs.

Example A12 includes the method of examples A07-A11, wherein theconfiguration is to indicate one or more TRB groups (TBGs) each TBG ofthe one or more TBGs is a set of consecutive TRBs, the resourceallocation is a time domain resource allocation, and the method furthercomprises: determining, by the baseband circuitry, a bitmap based on atime domain resource assignment field in the DCI, wherein the bitmap isto indicate one or more allocated TBGs; and determining, by the basebandcircuitry, the set of consecutive TRBs of the one or more allocated TBGsbased on the configuration and a bandwidth part (BWP) size.

Example A13 includes the method of examples A07-A12, wherein theresource allocation is a frequency domain resource allocation, and afrequency domain resource assignment field in the DCI does not includeone or more of a VRB-to-PRB mapping field, a PRB bundling size field,and a frequency hopping field.

Example A14 includes the method of examples A01-A13, wherein theresource allocation is a frequency domain resource allocation, and themethod further comprises:

determining, by the baseband circuitry based on a frequency domainresource assignment field in the DCI, an activated BWP from among one ormore configured BWPs; and

determining, by the baseband circuitry, a starting location of theactivated BWP based on an absolution frequency distance relative to areference point of the single carrier waveform.

Example A15 includes the method of example A14, wherein the methodfurther comprises: determining, by the baseband circuitry, a K valuebased on the frequency domain resource assignment field in the DCI or areceived configuration; and determining, by the baseband circuitry, abandwidth of the activated BWP based on a system BW and the K value.

Example A16 includes the method of examples A01-A15, wherein the singlecarrier waveform is a single carrier with frequency domain equalizer(SC-FDE) waveform.

Example A17 includes the method of examples A06-A16, wherein the higherlayer signaling includes minimum system information (MSI) signaling,remaining MSI (RMSI) signaling, other system information (OSI)signaling, or radio resource control (RRC) signaling.

Example B01 includes a method to be performed by a user equipment (UE)capable of communicating at frequencies above 52.6 gigahertz (GHz), themethod comprising: receiving Downlink Control Information (DCI);determining a resource allocation for a data transmission having asingle carrier waveform at or above 52.6 GHz based on informationincluded in the DCI; and communicating the data transmission accordingto the determined resource allocation, the communicating includingtransmitting or receiving the data transmission.

Example B02 includes the method of example B01, wherein the singlecarrier waveform includes a plurality of blocks where each block of theplurality of blocks includes a data portion and at least one guardinterval (GI) positioned before the data portion and/or at least one GIpositioned after the data portion, wherein the data portion of eachblock is divided into at least two sub-blocks, and wherein the datatransmission is to take place within a sub-block of a block of theplurality of blocks.

Example B03 includes the method of example B02, wherein no GI ispositioned between each sub-block of the at least two sub-blocks, onlyone GI is positioned between each sub-block of the at least twosub-blocks, or a GI is positioned before and after each sub-block of theat least two sub-blocks such that two GIs are positioned between eachsub-block.

Example B04 includes the method of example B03, wherein the GI is toinclude a unique word or a cyclic prefix.

Example B05 includes the method of example B04, wherein the resourceallocation is to indicate a sub-block in which the data transmission isto be transmitted or received.

Example B06 includes the method of example B05, further comprising:determining, based on higher layer signaling received, a GIconfiguration and one or more sub-block sizes, wherein the DCI is toindicate a selected sub-block size of the one or more sub-block sizes;and communicating the data transmission during a time periodcorresponding to the selected sub-block size.

Example B07 includes the method of examples B01-B06, wherein the singlecarrier waveform includes a plurality of time domain resource blocks(TRBs), and the method further comprises: determining, based on higherlayer signaling, a configuration that indicates N number of TRBs,wherein the DCI is to indicate one or more selected TRBs of the N numberof TRBs; and communicating the data transmission during one or more timeunits T_(c) corresponding to the one or more selected TRBs.

Example B08 includes the method of example B07, wherein theconfiguration is to indicate one or more TRBs of the N number of TRBs tobe used as GIs.

Example B09 includes the method of examples B07-B08, wherein the methodfurther comprises: determining the N number of TRBs based on a slotduration or a TRB size indicated by the configuration.

Example B10 includes the method of examples B07-B09, wherein theresource allocation is a time domain resource allocation, and the methodfurther comprises: determining, based on a time domain resourceassignment field in the DCI, a starting TRB relative to a start of aslot in which the data transmission is to be transmitted or received andan allocation length, wherein the allocation length is a number ofconsecutive TRBs counting from the starting TRB, and the number ofconsecutive TRBs are the one or more selected TRBs.

Example B11 includes the method of examples B07-B10, wherein theresource allocation is a time domain resource allocation, and the methodfurther comprises: Determining a bitmap based on a time domain resourceassignment field in the DCI, wherein the bitmap is to indicate the oneor more selected TRBs.

Example B12 includes the method of examples B07-B11, wherein theconfiguration is to indicate one or more TRB groups (TBGs) each TBG ofthe one or more TBGs is a set of consecutive TRBs, the resourceallocation is a time domain resource allocation, and the method furthercomprises: determining a bitmap based on a time domain resourceassignment field in the DCI, wherein the bitmap is to indicate one ormore allocated TBGs; and determining the set of consecutive TRBs of theone or more allocated TBGs based on the configuration and a bandwidthpart (BWP) size.

Example B13 includes the method of examples B07-B12, wherein theresource allocation is a frequency domain resource allocation, and afrequency domain resource assignment field in the DCI does not includeone or more of a VRB-to-PRB mapping field, a PRB bundling size field,and a frequency hopping field.

Example B14 includes the method of examples B01-B13, wherein theresource allocation is a frequency domain resource allocation, and themethod further comprises: determining, based on a frequency domainresource assignment field in the DCI, an activated BWP from among one ormore configured BWPs; and determining a starting location of theactivated BWP based on an absolution frequency distance relative to areference point of the single carrier waveform.

Example B15 includes the method of example B14, wherein the methodfurther comprises: determining a K value based on the frequency domainresource assignment field in the DCI or a received configuration; anddetermining a bandwidth of the activated BWP based on a system BW andthe K value.

Example B16 includes the method of examples B01-B15, wherein the singlecarrier waveform is a single carrier with frequency domain equalizer(SC-FDE) waveform.

Example B17 includes the method of examples B06-B16, wherein the higherlayer signaling includes minimum system information (MSI) signaling,remaining MSI (RMSI) signaling, other system information (OSI)signaling, or radio resource control (RRC) signaling.

Example C01 includes a method of operating a Radio Access Network (RAN)node capable of communicating at frequencies above 52.6 gigahertz (GHz),the method comprising:

generating Downlink Control Information (DCI) to indicate a resourceallocation for a data transmission, the data transmission having asingle carrier waveform at or above 52.6 GHz; and

communicating the DCI to a user equipment (UE) and for transmitting orreceiving the data transmission according to the resource allocation.

Example C01 includes the method of example C01, wherein the singlecarrier waveform includes a plurality of blocks where each block of theplurality of blocks includes a data portion and at least one guardinterval (GI) wherein the RAN node further comprises: inserting a uniqueword or a cyclic prefix into the at least one GI; partitioning the dataportion of each block into at least two sub-blocks; multiplexing anumber UEs within the data portion of each block such that each UE ofthe number of UEs is to communicate data within a respective sub-block,wherein the data transmission is to take place within a sub-block of ablock of the plurality of blocks, and the resource allocation is toindicate the sub-block in which the data transmission is to betransmitted or received; and generating the single carrier waveform suchthat no GI is to be positioned between each sub-block of the at leasttwo sub-blocks, only one GI is to be positioned between each sub-blockof the at least two sub-blocks, or a GI is to be positioned before andafter each sub-block of the at least two sub-blocks such that two GIsare positioned between each sub-block.

Example C03 includes the method of example C02, further comprising:generating a configuration to indicate a GI type and one or moresub-block sizes; generating the DCI to indicate a selected sub-blocksize of the one or more sub-block sizes indicated by the configuration;and transmitting the configuration to the UE via higher layer signaling,and for communicating the data transmission during a time periodcorresponding to the selected sub-block size.

Example C04 includes the method of example C01, wherein the plurality ofblocks and sub-blocks of the blocks of the plurality of blocks areexpressed in as a plurality of time domain resource blocks (TRBs) andwherein generating the configuration includes generating theconfiguration to indicate N number of TRBs including one or more TRBs ofthe N number of TRBs to be used as GIs, and generating the DCI toindicate one or more selected TRBs of the N number of TRBs; and whereinthe communicating includes communicating the data transmission duringone or more time units T_(c) corresponding to the one or more selectedTRBs.

Example C05 includes the method of example C04, wherein generating theDCI includes generating the DCI to include a time domain resourceassignment field including information for the UE to determine astarting TRB relative to a start of a slot in which the datatransmission is to be transmitted or received and an allocation length,wherein the allocation length is a number of consecutive TRBs countingfrom the starting TRB, and the number of consecutive TRBs are the one ormore selected TRBs.

Example C06 includes the method of example C04, wherein theconfiguration is to indicate one or more TRB groups (TBGs) each TBG ofthe one or more TBGs is a set of consecutive TRBs, and generating theDCI includes generating the DCI to include a time domain resourceassignment field including information for the UE to determine a bitmapbased on a time domain resource assignment field in the DCI, wherein thebitmap is to indicate one or more allocated TBGs wherein the set ofconsecutive TRBs of the one or more allocated TBGs is based on theconfiguration and a bandwidth part (BWP) size.

Example C07 includes the method of examples C04-C06, wherein generatingthe DCI includes generating the DCI to include a frequency domainresource assignment field and to not include one or more of a VRB-to-PRBmapping field, a PRB bundling size field, and a frequency hopping field.

Example C08 includes the method of example C07, wherein the frequencydomain resource assignment field in the DCI indicating an activated BWPfrom among one or more configured BWPs, and generating the DCI includesgenerating the DCI to include a K value, the K value to be used fordetermination of a starting location of the activated BWP based on anabsolution frequency distance relative to a reference point of thesingle carrier waveform, and for determination of a bandwidth of theactivated BWP.

Example C09 includes the method of examples C01-008, wherein the singlecarrier waveform is a single carrier with frequency domain equalizer(SC-FDE) waveform.

Example C10 includes the method of examples C03-C09, wherein the higherlayer signaling includes minimum system information (MSI) signaling,remaining MSI (RMSI) signaling, other system information (OSI)signaling, or radio resource control (RRC) signaling.

Example Z01 may include an apparatus comprising means to perform one ormore elements of a method described in or related to any of examplesA01-A17, B01-B17, C01-C10, or any other method or process describedherein.

Example Z02 may include one or more non-transitory computer-readablemedia comprising instructions to cause an electronic device, uponexecution of the instructions by one or more processors of theelectronic device, to perform one or more elements of a method describedin or related to any of examples A01-A17, B01-B17, C01-C10, or any othermethod or process described herein.

Example Z03 may include an apparatus comprising logic, modules, orcircuitry to perform one or more elements of a method described in orrelated to any of examples A01-A17, B01-B17, C01-C10, or any othermethod or process described herein.

Example Z04 may include a method, technique, or process as described inor related to any of examples A01-A17, B01-B17, C01-C10, or portions orparts thereof.

Example Z05 may include an apparatus comprising: one or more processorsand one or more computer-readable media comprising instructions that,when executed by the one or more processors, cause the one or moreprocessors to perform the method, techniques, or process as described inor related to any of examples A01-A17, B01-B17, C01-C10, or portionsthereof.

Example Z06 may include a signal as described in or related to any ofexamples A01-A17, B01-B17, C01-C10, or portions or parts thereof.

Example Z07 may include a datagram, packet, frame, segment, protocoldata unit (PDU), or message as described in or related to any ofexamples A01-A17, B01-B17, C01-C10, or portions or parts thereof, orotherwise described in the present disclosure.

Example Z08 may include a signal encoded with data as described in orrelated to any of examples A01-A17, B01-B17, C01-C10, or portions orparts thereof, or otherwise described in the present disclosure.

Example Z09 may include a signal encoded with a datagram, packet, frame,segment, protocol data unit (PDU), or message as described in or relatedto any of examples A01-A17, B01-B17, C01-C10, or portions or partsthereof, or otherwise described in the present disclosure. Example Z10may include an electromagnetic signal carrying computer-readableinstructions, wherein execution of the computer-readable instructions byone or more processors is to cause the one or more processors to performthe method, techniques, or process as described in or related to any ofexamples A01-A17, B01-B17, C01-C10, or portions thereof.

Example Z11 may include a computer program comprising instructions,wherein execution of the program by a processing element is to cause theprocessing element to carry out the method, techniques, or process asdescribed in or related to any of examples A01-A17, B01-B17, C01-C10, orportions thereof.

Example Z12 may include a signal in a wireless network as shown anddescribed herein. Example Z13 may include a method of communicating in awireless network as shown and described herein. Example Z14 may includea system for providing wireless communication as shown and describedherein. Example Z15 may include a device for providing wirelesscommunication as shown and described herein.

Any of the above-described examples may be combined with any otherexample (or combination of examples), unless explicitly statedotherwise. The terminology used herein is for the purpose of describingparticular embodiments only and is not intended to be limiting of thedisclosure. As used herein, the singular forms “a,” “an” and “the” areintended to include plural forms as well, unless the context clearlyindicates otherwise. It will be further understood that the terms“comprises” and/or “comprising,” when used in this specification,specific the presence of stated features, integers, steps, operations,elements, and/or components, but do not preclude the presence oraddition of one or more other features, integers, steps, operation,elements, components, and/or groups thereof. For the purposes of thepresent disclosure, the phrase “A and/or B” means (A), (B), or (A andB). For the purposes of the present disclosure, the phrase “A, B, and/orC” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B andC). The description may use the phrases “in an embodiment,” or “In someembodiments,” which may each refer to one or more of the same ordifferent embodiments. Furthermore, the terms “comprising,” “including,”“having,” and the like, as used with respect to embodiments of thepresent disclosure, are synonymous. The term “coupled” (or variantsthereof) may mean two or more elements are in direct physical orelectrical contact with one another, may mean that two or more elementsindirectly contact each other but still cooperate or interact with eachother, and/or may mean that one or more other elements are coupled orconnected between the elements that are said to be coupled with eachother. The term “communicatively coupled” may mean that two or moreelements may be in contact with one another by a means of communicationincluding through a wire or other interconnect connection, through awireless communication channel or ink, and/or the like.

The foregoing description provides illustration and description ofvarious example embodiments, but is not intended to be exhaustive or tolimit the scope of embodiments to the precise forms disclosed.Modifications and variations are possible in light of the aboveteachings or may be acquired from practice of various embodiments. Wherespecific details are set forth in order to describe example embodimentsof the disclosure, it should be apparent to one skilled in the art thatthe disclosure can be practiced without, or with variation of, thesespecific details. It should be understood, however, that there is nointent to limit the concepts of the present disclosure to the particularforms disclosed, but on the contrary, the intention is to cover allmodifications, equivalents, and alternatives consistent with the presentdisclosure and the appended claims.

1.-25. (canceled)
 26. A System-on-Chip (SoC) to be implemented in a userequipment (UE) capable of communicating at frequencies above 52.6gigahertz (GHz), the SoC comprising: interface circuitry; and basebandcircuitry coupled with the interface circuitry, the interface circuitryto communicatively couple the baseband circuitry to radiofrequency (RF)circuitry, the baseband circuitry to: determine, based on DownlinkControl Information (DCI) received via the RF circuitry, a resourceallocation for a data transmission scheduled by the DCI, the datatransmission having a single carrier waveform at or above 52.6 GHz, andcontrol the RF circuitry to transmit or receive the data transmissionaccording to the determined resource allocation.
 27. The SoC of claim26, wherein the single carrier waveform includes a plurality of blockswhere each block of the plurality of blocks includes a data portion andat least one guard interval (GI) positioned before the data portionand/or at least one GI positioned after the data portion, wherein thedata portion of each block is divided into at least two sub-blocks, andwherein the data transmission is to take place within a sub-block of ablock of the plurality of blocks, wherein the resource allocation is toindicate a sub-block in which the data transmission is to be transmittedor received.
 28. The SoC of claim 27, wherein no GI is to be positionedbetween each sub-block of the at least two sub-blocks, only one GI is tobe positioned between each sub-block of the at least two sub-blocks, ora GI is to be positioned before and after each sub-block of the at leasttwo sub-blocks, such that two GIs are positioned between each sub-block,wherein the GI is to include a unique word or a cyclic prefix.
 29. TheSoC of claim 28, wherein the baseband circuitry is further to:determine, based on higher layer signaling received via the RFcircuitry, a GI configuration and one or more sub-block sizes, whereinthe DCI is to indicate a selected sub-block size of the one or moresub-block sizes; and control the RF circuitry to transmit or receive thedata transmission during a time period corresponding to the selectedsub-block size.
 30. The SoC of claim 26, wherein the single carrierwaveform includes a plurality of time domain resource blocks (TRBs) andwherein the baseband circuitry is further to: determine, based on higherlayer signaling received via the RF circuitry, a configuration thatindicates N number of TRBs, wherein the DCI is to indicate one or moreselected TRBs of the N number of TRBs; and control the RF circuitry totransmit or receive the data transmission during one or more time unitsT_(c) corresponding to the one or more selected TRBs.
 31. The SoC ofclaim 30, wherein the configuration is to indicate one or more TRBs ofthe N number of TRBs to be used as GIs, and the baseband circuitry isfurther to: determine the N number of TRBs based on a slot duration or aTRB size indicated by the configuration.
 32. The SoC of claim 30,wherein the resource allocation is a time domain resource allocation,and the baseband circuitry is further to: determine, based on a timedomain resource assignment field in the DCI, a starting TRB relative toa start of a slot in which the data transmission is to be transmitted orreceived and an allocation length, wherein the allocation length is anumber of consecutive TRBs counting from the starting TRB, and thenumber of consecutive TRBs are the one or more selected TRBs.
 33. TheSoC of claim 30, wherein the configuration is to indicate one or moreTRB groups (TBGs) each TBG of the one or more TBGs is a set ofconsecutive TRBs, the resource allocation is a time domain resourceallocation, and the baseband circuitry is further to: determine a bitmapbased on a time domain resource assignment field in the DCI, wherein thebitmap is to indicate one or more allocated TBGs; and determine the setof consecutive TRBs of the one or more allocated TBGs based on theconfiguration and a bandwidth part (BWP) size.
 34. The SoC of claim 30,wherein the resource allocation is a frequency domain resourceallocation, and a frequency domain resource assignment field in the DCIdoes not include one or more of a VRB-to-PRB mapping field, a PRBbundling size field, and a frequency hopping field.
 35. The SoC of claim34, wherein the baseband circuitry is further to: determine, based on afrequency domain resource assignment field in the DCI, an activated BWPfrom among one or more configured BWPs; and determine a startinglocation of the activated BWP based on an absolution frequency distancerelative to a reference point of the single carrier waveform.
 36. TheSoC of claim 35, wherein the baseband circuitry is further to: determinea K value based on the frequency domain resource assignment field in theDCI or a received configuration; and determine a bandwidth of theactivated BWP based on a system BW and the K value.
 37. The SoC of claim26, wherein the single carrier waveform is a single carrier withfrequency domain equalizer (SC-FDE) waveform.
 38. The SoC of claim 29,wherein the higher layer signaling includes minimum system information(MSI) signaling, remaining MSI (RMSI) signaling, other systeminformation (OSI) signaling, or radio resource control (RRC) signaling.39. One or more non-transitory computer-readable media (NTCRM)comprising instructions, wherein execution of the instructions by one ormore processors is to cause a user equipment (UE) capable ofcommunicating at frequencies above 52.6 gigahertz (GHz) to: receiveDownlink Control Information (DCI); determine, based on the DCI, aresource allocation for a data transmission, the data transmissionhaving a single carrier with frequency domain equalizer (SC-FDE)waveform at or above 52.6 GHz; and control communication of the datatransmission according to the determined resource allocation, thecommunication including transmission or reception of the datatransmission.
 40. The one or more NTCRM of claim 39, wherein the SC-FDEincludes a plurality of time domain resource blocks (TRBs) and whereinexecution of the instructions is to cause the UE to: determine, based onreceived higher layer signaling, a configuration that indicates N numberof TRBs, wherein the DCI is to indicate one or more selected TRBs of theN number of TRBs, wherein the higher layer signaling includes minimumsystem information (MSI) signaling, remaining MSI (RMSI) signaling,other system information (OSI) signaling, or radio resource control(RRC) signaling; and control communication of the data transmissionduring one or more time units τ, corresponding to the one or moreselected TRBs.
 41. The one or more NTCRM of claim 40, wherein theconfiguration is to indicate one or more TRBs of the N number of TRBs tobe used as GIs, and wherein execution of the instructions is to causethe UE to: determine the N number of TRBs based on a slot duration or aTRB size indicated by the configuration.
 42. The one or more NTCRM ofclaim 40, wherein the resource allocation is a time domain resourceallocation, and wherein execution of the instructions is to cause the UEto: determine, based on a time domain resource assignment field in theDCI, a starting TRB relative to a start of a slot in which the datatransmission is to be transmitted or received and an allocation length,wherein the allocation length is a number of consecutive TRBs countingfrom the starting TRB, and the number of consecutive TRBs are the one ormore selected TRBs.
 43. The one or more NTCRM of claim 40, wherein theconfiguration is to indicate one or more TRB groups (TBGs) each TBG ofthe one or more TBGs is a set of consecutive TRBs, the resourceallocation is a time domain resource allocation, and wherein executionof the instructions is to cause the UE to: determine a bitmap based on atime domain resource assignment field in the DCI, wherein the bitmap isto indicate one or more allocated TBGs; and determine the set ofconsecutive TRBs of the one or more allocated TBGs based on theconfiguration and a bandwidth part (BWP) size.
 44. The one or more NTCRMof claim 40, wherein the resource allocation is a frequency domainresource allocation, and a frequency domain resource assignment field inthe DCI does not include one or more of a VRB-to-PRB mapping field, aPRB bundling size field, and a frequency hopping field, and execution ofthe instructions is to cause the UE to: determine, based on a frequencydomain resource assignment field in the DCI, an activated BWP from amongone or more configured BWPs; and determine a starting location of theactivated BWP based on an absolution frequency distance relative to areference point of the SC-FDE.
 45. The one or more NTCRM of claim 44,wherein execution of the instructions is to cause the UE to: determine aK value based on the frequency domain resource assignment field in theDCI or a received configuration; and determine a bandwidth of theactivated BWP based on a system BW and the K value.
 46. A Radio AccessNetwork (RAN) node capable of communicating at frequencies above 52.6gigahertz (GHz), the RAN node comprising: processor circuitry togenerate Downlink Control Information (DCI) to indicate a resourceallocation for a data transmission, the data transmission having asingle carrier waveform at or above 52.6 GHz; and interface circuitrycommunicatively coupled with the processor circuitry, the interfacecircuitry to: communicate the DCI to a user equipment (UE); andcommunicate the data transmission according to the resource allocation.47. The RAN node of claim 46, wherein the single carrier waveformincludes a plurality of blocks where each block of the plurality ofblocks includes a data portion and at least one guard interval (GI),wherein the processor circuitry is further to: insert a unique word or acyclic prefix into the at least one GI; partition the data portion ofeach block into at least two sub-blocks; and multiplex a number UEswithin the data portion of each block such that each UE of the number ofUEs is to communicate data within a respective sub-block, wherein thedata transmission is to take place within a sub-block of a block of theplurality of blocks, and the resource allocation is to indicate thesub-block in which the data transmission is to be transmitted orreceived, and the interface circuitry is further to generate the singlecarrier waveform such that no GI is to be positioned between eachsub-block of the at least two sub-blocks, only one GI is to bepositioned between each sub-block of the at least two sub-blocks, or aGI is to be positioned before and after each sub-block of the at leasttwo sub-blocks such that two GIs are positioned between each sub-block.48. The RAN node of claim 47, wherein: the processor circuitry isfurther to: generate a configuration to indicate a GI type and one ormore sub-block sizes, and generate the DCI to indicate a selectedsub-block size of the one or more sub-block sizes indicated by theconfiguration; and the interface circuitry is further to: transmit theconfiguration to the UE via higher layer signaling, and communicate thedata transmission during a time period corresponding to the selectedsub-block size.
 49. The RAN node of claim 46, wherein the plurality ofblocks and sub-blocks of the blocks of the plurality of blocks areexpressed in as a plurality of time domain resource blocks (TRBs) andwherein: the processor circuitry is further to: generate theconfiguration to indicate N number of TRBs including one or more TRBs ofthe N number of TRBs to be used as GIs, and generate the DCI to indicateone or more selected TRBs of the N number of TRBs; and the interfacecircuitry is further to communicate the data transmission during one ormore time units T_(c) corresponding to the one or more selected TRBs.50. The RAN node of claim 49, wherein the processor circuitry is furtherto: generate the configuration to indicate one or more TRB groups (TBGs)each TBG of the one or more TBGs is a set of consecutive TRBs; andgenerate the DCI to include a time domain resource assignment fieldincluding information for the UE to determine a bitmap based on a timedomain resource assignment field in the DCI, wherein the bitmap is toindicate one or more allocated TBGs wherein the set of consecutive TRBsof the one or more allocated TBGs is based on the configuration and abandwidth part (BWP) size.